Memory system design using buffer(s) on a mother board
US-2016364347-A1 · Dec 15, 2016 · US
US10318474B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-10318474-B1 |
| Application number | US-201514754865-A |
| Country | US |
| Kind code | B1 |
| Filing date | Jun 30, 2015 |
| Priority date | Jun 30, 2015 |
| Publication date | Jun 11, 2019 |
| Grant date | Jun 11, 2019 |
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A storage node such as a storage array or storage server has storage controllers with heterogeneous parallel processors. The CPUs may be used to perform read and write operations. GPUs are used to produce transformed data from raw data. The GPUs may be used to perform various analytic calculations. The GPUs may be interconnected via dedicated communication links.
Opening claim text (preview).
What is claimed is: 1. An apparatus comprising: at least one non-transitory data storage device; and at least one storage controller adapted to present a logical storage device to a host device, maintain a mapping between the logical storage device and the at least one non-transitory data storage device; and provide the host device with access to the at least one non-transitory data storage device in response to a request which references the logical storage device, the at least one storage controller comprising a heterogeneous parallel processor comprising at least one central processing unit and at least one graphics processing unit. 2. The apparatus of claim 1 further comprising a shared memory cache, and wherein the at least one storage controller comprises at least one front end controller which has access to the shared memory cache and presents the logical storage device, and at least one back end controller which has access to the shared memory cache and the at least one non-transitory data storage device. 3. The apparatus of claim 1 comprising a plurality of heterogeneous parallel processors comprising graphics processing units which are interconnected by at least one dedicated communication link. 4. The apparatus of claim 1 wherein the at least one graphics processing unit is adapted to generate transformed data from raw data. 5. The apparatus of claim 4 wherein the raw data and the corresponding transformed data are stored on the at least one non-transitory data storage device. 6. The apparatus of claim 5 wherein the at least one central processing unit is adapted to provide extents of the transformed data stored on the at least one non-transitory data storage device to the host device. 7. The apparatus of claim 4 wherein the transformed data is provided to the host device by the at least one storage controller. 8. The apparatus of claim 1 wherein the at least one graphics processing unit is adapted to perform analytic calculations to support an application running on the host device. 9. The apparatus of claim 8 wherein the analytic calculations comprise pattern matching. 10. The apparatus of claim 1 wherein the at least one graphics processing unit is adapted to perform analytic calculations to support internal operations. 11. The apparatus of claim 1 wherein the at least one graphics processing unit is adapted to perform analytic calculations to support an unsupervised neural-net algorithm for storage tiering. 12. A method comprising: storing data on at least one non-transitory data storage device; with at least one storage controller: presenting a logical storage device to a host device; maintain a mapping between the logical storage device and the at least one non-transitory data storage device; and providing the host device with access to the at least one non-transitory data storage device in response to a request which references the logical storage device, the at least one storage controller comprising a heterogeneous parallel processor with at least one central processing unit and at least one graphics processing unit; and selectively performing calculations with ones of the at least one graphics processing unit. 13. The method of claim 12 further comprising performing distributed calculations by multiple graphics processing units via at least one dedicated communication link. 14. The method of claim 12 further comprising the at least one graphics processing unit generating transformed data from raw data. 15. The method of claim 14 further comprising storing the raw data and the corresponding transformed data on the at least one non-transitory data storage device. 16. The method of claim 12 further comprising the at least one graphics processing unit performing analytic calculations to support an application running on the host device. 17. The method of claim 12 further comprising the at least one graphics processing unit performing pattern matching. 18. The method of claim 12 further comprising the at least one graphics processing unit performing analytic calculations to support internal operations. 19. The method of claim 12 further comprising the at least one graphics processing unit performing analytic calculations to support an unsupervised neural-net algorithm for storage tiering.
for peripheral storage systems, e.g. disk cache · CPC title
with a shared cache · CPC title
Plural cache memories · CPC title
Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all · CPC title
Access to shared memory · CPC title
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