Error handling
US-2026011394-A1 · Jan 8, 2026 · US
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Padilla Renato C patents
Padilla Renato C is listed as an inventor on 108 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Padilla Renato C |
| Total patents | 108 |
| First publication | Dec 17, 2015 |
| Latest publication | Jan 8, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Error handling
US-12451209-B2 · Oct 21, 2025 · US
Diagonal page mapping in memory systems
US-2025306796-A1 · Oct 2, 2025 · US
Diagonal page mapping in memory systems
US-12353753-B2 · Jul 8, 2025 · US
Memory devices and systems including hybrid cache, and related methods
US-2025013364-A1 · Jan 9, 2025 · US
Program continuation strategies after memory device power loss
US-2025006281-A1 · Jan 2, 2025 · US
Memory devices and systems including static and dynamic caches, and related methods
US-12131020-B2 · Oct 29, 2024 · US
Program continuation strategies after memory device power loss
US-12119068-B2 · Oct 15, 2024 · US
Accelerating configuration updates for memory devices
US-2024257887-A1 · Aug 1, 2024 · US
Accelerating configuration updates for memory devices
US-11984174-B2 · May 14, 2024 · US
Recent patents
Latest publications not already listed above.
Optimized storage charge loss management
US-11923030-B2 · Mar 5, 2024 · US
Error handling
US-2023393922-A1 · Dec 7, 2023 · US
Selective read disturb sampling
US-11810627-B2 · Nov 7, 2023 · US
Redundant array of independent NAND for a three-dimensional memory array
US-11797383-B2 · Oct 24, 2023 · US
Power-on-time based data relocation
US-11789862-B2 · Oct 17, 2023 · US
Adaptive temperature compensation for memory devices
US-11756625-B2 · Sep 12, 2023 · US
Program continuation strategies after memory device power loss
US-2023268014-A1 · Aug 24, 2023 · US
Operation of mixed mode blocks
US-11721404-B2 · Aug 8, 2023 · US
Workload adaptive scans for memory sub-systems
US-11715541-B2 · Aug 1, 2023 · US
Open block management using storage charge loss margin checking
US-11715531-B2 · Aug 1, 2023 · US
Offset memory component automatic calibration (autocal) error recovery for a memory sub-system
US-11715530-B2 · Aug 1, 2023 · US
Dynamic program-verify voltage adjustment for intra-block storage charge loss uniformity
US-11687452-B2 · Jun 27, 2023 · US
Memory management
US-11586357-B2 · Feb 21, 2023 · US
Diagonal page mapping in memory systems
US-2023049877-A1 · Feb 16, 2023 · US
Diagonal page mapping in memory systems
US-2022391127-A1 · Dec 8, 2022 · US
Optimized storage charge loss management
US-2022392561-A1 · Dec 8, 2022 · US
Selective read disturb sampling
US-2022383962-A1 · Dec 1, 2022 · US
Diagonal page mapping in memory systems
US-11507304-B1 · Nov 22, 2022 · US
Workload adaptive scans for memory sub-systems
US-2022351796-A1 · Nov 3, 2022 · US
Optimized storage charge loss management
US-2022310190-A1 · Sep 29, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 107 |
| Micron Technology Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C16/26 | 45 |
| G11C16/10 | 42 |
| G06F12/0246 | 42 |
| G06F3/0679 | 36 |
| G06F3/064 | 36 |