Method for estimating stress of electronic component

Patent metadata

Field	Value
Publication number	US-10317296-B2
Application number	US-201614988747-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	Jun 25, 2015
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A method for estimating stress of an electronic component. An electronic component including first and second elements and conductive bumps is provided. Each conductive bump has two surfaces connected to the first and second elements respectively. Two adjacent conductive bumps have a pitch therebetween. The conductive bumps includes a first conductive bump and second conductive bumps. A stress value of the first conductive bump related to a testing parameter is calculated. A stress value of each second conductive bump related to the testing parameter is calculated according to a first calculating formula. The first calculating formula is
σ 2 = L D - 2 ⁢ r ⁢ σ 1 ,
σ 2 is the stress of each second conductive bump, L is a beeline distance between each second conductive bump and the first conductive bump, D is an average value of the pitches of the conductive bumps, r is a radius of each surface, and σ 1 is the stress value of the first conductive bump.

First claim

What is claimed is:

1. A testing method for an electronic component within a semiconductor package, the method comprising:
providing an electronic component comprising a first element, a second element and a plurality of conductive bumps, wherein each of the conductive bumps has two opposite surfaces, the two surfaces are respectively connected to the first element and the second element, a pitch is between adjacent two of the conductive bumps, and the conductive bumps comprises a first conductive bump and a plurality of second conductive bumps;
applying a testing parameter associated with a testing condition variation to the electronic component to obtain a testing result;
calculating a stress value of the first conductive bump based on the testing result;
calculating a stress value of each of the second conductive bumps by a processor, wherein the processor uses a first calculating formula to calculate the stress value of each of the second conductive bumps related to the testing parameter, the first calculating formula is

σ
2

=

L

D
-

2
⁢
r

⁢

σ
1

,

σ 2 is the stress value of each of the second conductive bumps, L is a beeline distance between each of the second conductive bumps and the first conductive bump, D is an average of the pitches of the conductive bumps, r is a radius of each of the surfaces, and σ 1 is the stress value of the first conductive bump; and
determining the stress value of each of the second conductive bumps without having to measure the stress value of each of the second conductive bumps, and estimating a lifetime of each of the second conductive bumps according to the stress value of each of the second conductive bumps.

2. The method according to claim 1 , wherein the first conductive bump is located in a geometric center of the electronic component.

3. The method according to claim 1 , wherein the testing parameter is a temperature variation or a voltage variation.

4. The method according to claim 1 , wherein the step of calculating the stress value of the first conductive bump related to the testing parameter comprises:
calculating the stress value of the first conductive bump related to the testing parameter according to a second calculating formula, wherein the second calculating formula is

σ
1

=

E
solder

⁡

(

D
-

2
⁢
r

)

⁢
ΔαΔ
⁢

⁢
T

4
⁢

(

1
+

⁢

∈
solder

)

⁢
h

,

E solder is a Young's modulus of each of the conductive bumps, ∈ solder is a Poisson ratio of each of the conductive bumps, Δα is a difference between a coefficient of thermal expansion (CTE) of the first element and a CTE of the second element, h is a distance between the first element and the second element, and ΔT is the testing parameter.

5. A testing method for testing an electronic component within a semiconductor package, the method comprising:
providing an electronic component comprising a first element, a second element, a plurality of conductive bumps, and a molding compound, wherein the molding compound is disposed between the first element and the second element and covers the conductive bumps, each of the conductive bumps has two opposite surfaces, the two surfaces are respectively connected to the first element and the second element, a pitch is between adjacent two of the conductive bumps, and the conductive bumps comprises a first conductive bump and a plurality of second conductive bumps;
applying a testing parameter associated with a testing condition variation to the electronic component to obtain a testing result;
calculating a stress value of the first conductive bump based on the testing result;
calculating a stress value of each of the second conductive bumps by a processor, wherein the processor uses a fourth calculating formula to calculate the stress value of each of the second conductive bumps related to the testing parameter, the fourth calculating formula is

σ
2

=

L

D
-

2
⁢
r

⁢

(

σ
1

-

(

E
solder

⁢

α
solder

+

E
underfill

⁢

α
underfill

)

⁢
Δ
⁢

Assignees

• Winbond Electronics Corp

Inventors

• Chen Chien-Chang
• Lu Horng-Shing

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G01N25/16

  by investigating thermal coefficient of expansion · CPC title

• G01L1/005 Primary

  by electrical means and not provided for in G01L1/06 - G01L1/22 · CPC title

• H01L22/12

  Electricity · mapped topic