Calibration for time-interleaved analog-to-digital converters and signal generators therefor

Patent metadata

Field	Value
Publication number	US-10312927-B1
Application number	US-201815935988-A
Country	US
Kind code	B1
Filing date	Mar 26, 2018
Priority date	Mar 26, 2018
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.

First claim

What is claimed is:

1. A signal generator for calibrating a time-interleaved analog-to-digital converter (ADC) circuit having a plurality of channels, comprising:
a pattern generator configured to receive a periodic signal and output a bitstream based on the periodic signal, wherein the bitstream:
has a bit pattern with a total number of bits that shares no common factor with a number of the channels; and
includes a relatively lower frequency component combined with a relatively higher frequency component; and

a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream, wherein the signal generator is configured to output a double sawtooth signal as the waveform.

2. The signal generator of claim 1 , wherein the total number of bits for one period of the double sawtooth signal is 127.

3. The signal generator of claim 1 , wherein the total number of bits for one period of the double sawtooth signal is 63 and wherein the number of the channels is 8.

4. The signal generator of claim 1 , wherein the bitstream for the double sawtooth signal comprises at least one of:
a first repeating bit pattern of {0,1,0} for a ramping down portion of the double sawtooth signal; or
a second repeating bit pattern of {1,0,1} for a ramping up portion of the double sawtooth signal.

5. The signal generator of claim 1 , wherein:
the pattern generator comprises a multiplexer having a plurality of inputs coupled to outputs of a plurality of waveform bitstream generating circuits and an output coupled to the output of the pattern generator; and
the multiplexer is configured to select one of the outputs of the plurality of waveform bitstream generating circuits as the bitstream output by the pattern generator.

6. The signal generator of claim 5 , wherein the plurality of waveform bitstream generating circuits is configured to generate at least one of a first bitstream for a double sawtooth signal, a second bitstream for a single sawtooth signal, or a third bitstream based on a linear feedback shift register (LFSR) sequence.

7. The signal generator of claim 1 , wherein the pattern generator comprises a delay tuning circuit configured to variably delay the periodic signal or a version of the periodic signal.

8. The signal generator of claim 1 , wherein the pattern generator comprises a frequency dividing circuit configured to divide a frequency of the periodic signal or of a version of the periodic signal to generate a lower frequency periodic signal.

9. An integrated circuit (IC) comprising the signal generator of claim 1 and the time-interleaved analog-to-digital converter circuit, wherein an output of the conversion circuit is selectively coupled to an input of the time-interleaved analog-to-digital converter circuit.

10. The integrated circuit of claim 9 , wherein the signal generator and the time-interleaved analog-to-digital converter circuit receive power from a same power supply rail.

11. The integrated circuit of claim 9 , wherein the periodic signal the pattern generator is configured to receive is a sampling clock signal for the time-interleaved analog-to-digital converter circuit.

12. A method of generating a waveform for calibrating a time-interleaved analog-to-digital converter (ADC) circuit having a plurality of channels, comprising:
receiving a periodic signal;
generating a bitstream based on the periodic signal, wherein the bitstream:
has a bit pattern with a total number of bits that shares no common factor with a number of the channels; and
includes a relatively lower frequency component combined with a relatively higher frequency component; and

generating the waveform based on the bitstream, wherein the waveform comprises a double sawtooth signal.

13. The method of claim 12 , wherein the total number of bits for one period of the double sawtooth signal is 127.

14. The method of claim 12 , wherein the total number of bits for one period of the double sawtooth signal is 63 and wherein the number of the channels is 8.

15. The method of claim 12 , wherein the bitstream for the double sawtooth signal comprises at least one of:
a first repeating bit pattern of {0,1,0} for a ramping down portion of the double sawtooth signal; or
a second repeating bit pattern of {1,0,1} for a ramping up portion of the double sawtooth signal.

16. The method of claim 12 , wherein generating the bitstream comprises selecting one of a plurality of different bitstreams as the bitstream.

17. The method of claim 16 , wherein the plurality of different bitstreams comprises at least one of a first bitstream for a double sawtooth signal, a second bitstream for a single sawtooth signal, or a third bitstream based on a linear feedback shift register (LFSR) sequence.

18. The method of claim 12 , wherein generating the bitstream comprises variably delaying the periodic signal or a version of the periodic signal.

19. The method of claim 12 , wherein generating the bitstream comprises dividing a frequency of the periodic signal or of a version of the periodic signal to generate a lower frequency periodic signal.

20. The method of claim 12 , wherein the periodic signal comprises a sampling clock signal for the time-interleaved analog-to-digital converter circuit.

21. An apparatus for generating an analog waveform for calibrating a time-interleaved analog-to-digital converter (ADC) circuit having a plurality of channels, the apparatus comprising:
means for generating a digital bitstream based on a periodic signal, wherein the digital bitstream:
has a bit pattern with a total number of bits that shares no common factor with a number of the channels; and
includes a relatively lower frequency component combined with a relatively higher frequency component; and

means for generating the analog waveform based on the bitstream, wherein the analog waveform comprises a double sawtooth signal.

Assignees

• Qualcomm Inc

Inventors

• Mirhaj Seyed Arash
• Dagher Elias
• Tang Yongjian
• Alladi Dinesh
• Ensafdaran Masoud
• Sun Lei
• Meruva Anand
• Guo Yuhua
• Sivakumar Balasubramanian

Classifications

• H03K4/08

  having sawtooth shape · CPC title

• H03M1/1033 Primary

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title

• H03M1/1014

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title