Semiconductor Fin FET device with epitaxial source/drain

Patent metadata

Field	Value
Publication number	US-9859427-B2
Application number	US-201615280216-A
Country	US
Kind code	B2
Filing date	Sep 29, 2016
Priority date	Sep 4, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first fin structure disposed over the substrate, extending in a first direction, and including a first channel region and a first source/drain region;
a second fin structure disposed over the substrate, extending in the first direction, and including a second channel region and a second source/drain region;
a gate structure disposed over at least a portion of the first fin structure and the second fin structure, and extending in a second direction crossing the first direction, the first and second channel regions being beneath the gate structure and the first and second source/drain regions being outside of the gate structure;
a first strain material layer disposed over the first source/drain region and a second strain material layer disposed over the second source/drain region, the first and second strain material layers providing stress to the first and second channel regions, respectively; and
a contact layer wrapping around the first and second strain material layers,
wherein the first strain material layer is separated from the second strain material layer, and
widths of the first and second source/drain regions are smaller than widths of the first and second channel regions measured in the second direction.

2. The semiconductor device of claim 1 , wherein:
the first fin structure further includes a first well region below the first channel region and the second fin structure further includes a second well region below the second channel region, and
the first and second channel regions are made of a different material from the first and second well regions.

3. The semiconductor device of claim 1 , further comprising an insulating layer separating the gate structure and the contact layer,
wherein the first and second fin structures further include mask layers under the insulating layer, respectively, and do not have the mask layers in the first and second channel regions and the first and second source/drain regions.

4. The semiconductor device of claim 1 , wherein a width of the first source/drain region is 40% to 60% of a width of the first channel region.

5. The semiconductor device of claim 1 , wherein the contact layer comprises:
a first conductive layer disposed over the first strain material; and
a second conductive layer disposed over the second strain material.

6. The semiconductor device of claim 5 , wherein the first conductive layer is not direct contact with the second conductive layer.

7. The semiconductor device of claim 1 , further comprising a contact plug touching both upper portions of the first and second source/drain regions and substantially the entire side walls of the first and second source/drain regions, forming a “wrap-around” contact.

8. The semiconductor device of claim 1 , wherein the contact layer includes one or more layers of metal selected from the group consisting of Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, and CoSi.

9. A semiconductor device, comprising:
a substrate;
a first fin structure disposed over the substrate and including a first channel region and a first source/drain region;
a second fin structure disposed over the substrate and including a second channel region and a second source/drain region;
a gate structure disposed over at least a portion of the first fin structure and the second fin structure, the first and second channel regions being beneath the gate structure and the first and second source/drain regions being outside of the gate structure;
a first strain material layer disposed over the first source/drain region and a second strain material layer disposed over the second source/drain region, the first and second strain material layers providing stress to the first and second channel regions, respectively;
a contact layer wrapping around the first and second strain material layers; and
an insulating layer separating the gate structure and the contact layer,
wherein the first and second fin structures further include mask layers under the insulating layer, respectively, and do not have the mask layers in the first and second channel regions and the first and second source/drain regions.

10. The semiconductor device of claim 9 , wherein the first strain material layer is separated from the second strain material layer.

11. The semiconductor device of claim 9 , wherein widths of the first and second source/drain regions are smaller than widths of the first and second channel regions.

12. The semiconductor device of claim 9 , wherein:
the first fin structure further includes a first well region below the first channel region and the second fin structure further includes a second well region below the second channel region, and
the first and second channel regions are made of a different material from the first and second well regions.

13. The semiconductor device of claim 9 , further comprising an insulating layer separating the gate structure and the contact layer,
wherein the first and second fin structures further include mask layers under the insulating layer and do not have the mask layers in the first and second channel regions and the first and second source/drain regions.

14. The semiconductor device of claim 9 , wherein a width of the first source/drain region is 40% to 60% of a width of the first channel region.

15. The semiconductor device of claim 9 , wherein the contact layer comprises:
a first conductive layer disposed over the first strain material;
a second conductive layer disposed over the second strain material; and
a conductive material to wrap the first and second conductive layers and fill a space between the first and second source/drain regions.

16. The semiconductor device of claim 9 , wherein the first conductive layer is not direct contact with the second conductive layer.

17. The semiconductor device of claim 9 , further comprising a contact plug touching both upper portions of the first and second source/drain regions and substantially the entire side walls of the first and second source/drain regions, forming a “wrap-around” contact.

18. A semiconductor device, comprising:
a substrate;
a fin structure disposed over the substrate, extending in a first direction and including a channel region and a source/drain region;
a gate structure disposed over at least a portion of the fin structure and extending in a second direction crossing the first direction, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure;
a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region; and
a contact layer wrapping around the first strain material layer,
wherein a width of the source/drain region is smaller than a width of the channel region measured in the second direction.

19. The semiconductor device of claim 18 , further comprising an insulating layer separating the gate structure and the contact layer,
wherein the fin structure further includes a mask layer under the insulating layer and does not have the mask layer in the channel region and the source/drain region.

20. The semiconductor device of claim 18 , further comprising a contact plug touching both upper portion of the source/drain region and substantially the entire side walls of the source/drain region, forming a “wrap-around” contact.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Tawain Semiconductor Mfg Co Ltd

Inventors

• Chiang Hung-Li
• Peng Cheng-Yi
• Sheu Jyh-Cherng
• Yeo Yee-Chia

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L29/0649

  Electricity · mapped topic