FinFET and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9634104-B2
Application number	US-201514711170-A
Country	US
Kind code	B2
Filing date	May 13, 2015
Priority date	Jan 31, 2012
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A method of fabricating a fin field effect transistor (FinFET) includes forming a first fin and a second fin extending upward from a substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, selectively forming a bulbous epitaxial layer covering a portion of each fin, annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide and depositing a metal layer at least in the cavity. The first fin and the second fin are adjacent. A portion of the first fin and a portion of the second fin extend beyond the top surface of the insulation layer. The bulbous epitaxial layer defines an hourglass shaped cavity between adjacent fins.

First claim

What is claimed is:

1. A method of fabricating a fin field effect transistor (FinFET) comprising:
forming a first fin and a second fin extending upward from a substrate major surface to a first height, wherein the first fin and the second fin are adjacent;
forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, wherein a portion of the first fin and a portion of the second fin extend beyond the top surface of the insulation layer;
selectively forming a bulbous epitaxial layer covering a portion of each fin, wherein the bulbous epitaxial layer defines an hourglass shaped cavity between the first and second fins, wherein the hourglass cavity at its narrowest point provides a gap between the bulbous epitaxial layer of the first fin and the bulbous epitaxial layer of the second fin;
depositing a first metal layer on the bulbous epitaxial layer;
annealing the substrate and the first metal layer to convert at least a portion of the bulbous epitaxial layer and at least a portion of the first metal layer to silicide;
after the annealing, etching a portion of the first metal material in the hourglass cavity, wherein the portion is unreacted first metal material; and
after annealing, depositing a second metal layer within the hourglass cavity.

2. The method of claim 1 , wherein annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide comprises performing a first rapid thermal anneal to the substrate at a temperature between about 200° C. to 300° C.

3. The method of claim 2 , wherein the first rapid anneal to the substrate is performed for a time between about 10 seconds to 30 seconds.

4. The method of claim 2 , wherein annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide further comprises performing a second rapid thermal anneal to the substrate at a temperature between about 300° C. to 500° C.

5. The method of claim 4 , wherein the second rapid anneal to the substrate is performed for a time between about 30 seconds to 60 seconds.

6. A method of fabricating a fin field effect transistor (FinFET) comprising:
forming a first fin and a second fin, wherein:
the first fin is adjacent to the second fin, and
the first fin and second fin extend upward from a substrate major surface;

selectively forming a bulbous epitaxial layer covering each of the first fin and the second fin, wherein a separation between the bulbous epitaxial layer of the first fin and the bulbous epitaxial layer of the second fin defines an hourglass shaped cavity between the first fin and the second fin;
converting at least a portion of the bulbous epitaxial layer to silicide, wherein after the converting, a gap remains between a narrowest point between the silicide of the first fin and the silicide of the second fin; and
after converting, depositing a metal layer over the silicide, within the cavity and within the gap.

7. The method of claim 6 , wherein selectively forming the bulbous epitaxial layer comprises:
selectively growing an epitaxial layer covering each fin, wherein the epitaxial layer comprises a plurality of edges; and
rounding each of the edges of the epitaxial layer.

8. The method of claim 7 , wherein rounding each of the edges of the epitaxial layer comprises annealing the substrate to have each fin covered by the bulbous epitaxial layer.

9. The method of claim 8 , wherein annealing the substrate to have each fin covered by the bulbous epitaxial layer is performed at a temperature between about 800° C. to 1100° C.

10. The method of claim 8 , wherein annealing the substrate to have each fin covered by the bulbous epitaxial layer is performed under a pressure of about 5 Torr to 760 Torr.

11. The method of claim 8 , wherein annealing the substrate to have each fin covered by the bulbous epitaxial layer is performed at a flow rate of about 5 sccm to 200 sccm.

12. The method of claim 8 , wherein annealing the substrate to have each fin covered by the bulbous epitaxial layer is performed using H 2 or D 2 as a reaction gas.

13. The method of claim 12 , further comprising flowing a carrier gas over the substrate.

14. The method of claim 13 , wherein the carrier gas comprises N 2 , He, or Ar.

15. A method of fabricating a fin field effect transistor (FinFET) comprising:
forming a first fin and a second fin, wherein:
the first fin is adjacent to the second fin, and
the first fin and second fin extend upward from a substrate major surface;

selectively forming a first bulbous epitaxial layer to partially cover the first fin and a second bulbous epitaxial layer to partially cover the second fin, wherein the bulbous epitaxial layer defines an hourglass shaped cavity between each fin, and the cavity comprises a lower portion defining by a lower portion of a sidewall the first bulbous epitaxial layer and a lower portion of a sidewall of the second bulbous epitaxial layer;
forming a first metal material over the bulbous epitaxial layer including directly on the lower portion of the sidewall of the first bulbous epitaxial layer and directly on the lower portion of the sidewall of the second bulbous epitaxial layer; and
annealing the substrate to at least partially convert the bulbous epitaxial layer bordering the lower portion of the cavity to silicide using the first metal material.

16. The method of claim 15 , wherein annealing the substrate to partially convert the bulbous epitaxial layer to silicide comprises performing a first rapid thermal anneal to the substrate at a temperature between about 200° C. to 300° C.

17. The method of claim 16 , wherein the first rapid thermal anneal to the substrate is performed for a time between about 10 seconds to 20 seconds.

18. The method of claim 16 , wherein annealing the substrate to partially convert the bulbous epitaxial layer to silicide further comprises performing a second rapid thermal anneal performed at a temperature between about 300° C. to 500° C.

19. The method of claim 18 , wherein the second rapid thermal anneal to the substrate is performed for a time between about 10 seconds to 30 seconds.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chao Donald Y
• Chen Hou-Yu
• Yang Shyh-Horng

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/38

  characterised by treatments done after the formation of the materials · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title