Diode structure and method for gate all around silicon nanowire technologies

Patent metadata

Field	Value
Publication number	US-8927397-B2
Application number	US-201313761453-A
Country	US
Kind code	B2
Filing date	Feb 7, 2013
Priority date	Feb 7, 2013
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

First claim

What is claimed is:

1. A method of fabricating an electronic device, comprising the steps of:
providing a semiconductor-on-insulator (SOI) wafer having a SOI layer over a buried oxide (BOX);
patterning at least one first set of nanowires and first set pads in the SOI layer and at least one second set of nanowires and second set of pads in the SOI layer, wherein the first set of pads are attached at opposite ends of the first set of nanowires in a ladder-like configuration and wherein the second set of pads are attached at opposite ends of the second set of nanowires in a ladder-like configuration;
selectively forming a conformal gate dielectric layer surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device;
forming a first metal gate stack on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration; and
forming a second metal gate stack surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

2. The method of claim 1 , further comprising the step of:
doping the second set of nanowires.

3. The method of claim 2 , wherein the second set of nanowires are doped with an n-type or p-type dopant.

4. The method of claim 1 , wherein the conformal gate dielectric layer comprises a high-k dielectric material.

5. The method of claim 4 , wherein the high-k dielectric material comprises hafnium oxide.

6. The method of claim 1 , wherein the conformal gate dielectric layer is deposited using chemical vapor deposition.

7. The method of claim 1 , wherein the conformal gate dielectric layer is deposited to a thickness of from about 1 nm to about 5 nm.

8. The method of claim 1 , further comprising the step of:
depositing a conformal gate metal layer 1) on the conformal gate dielectric layer over the portion of the first set of nanowires that serves as the channel region of the transistor device and 2) directly on the portion of the second set of nanowires that serves as the channel region of the diode device.

9. The method of claim 8 , wherein the conformal gate metal layer comprises one or more of titanium nitride and tantalum nitride.

10. The method of claim 8 , wherein the conformal gate metal layer is deposited to a thickness of from about 5 nm to about 20 nm.

11. The method of claim 1 , further comprising the steps of:
forming a first dummy gate over the portion of each of the first set of nanowires that serves as the channel region of the transistor device;
forming a second dummy gate over the portion of each of the second set of nanowires that serves as the channel region of the diode device;
depositing a filler layer around the first dummy gate and the second dummy gate;
removing the first dummy gate to expose the portion of the first set of nanowires that serves as the channel region of the transistor device within a first trench in the filler layer; and
removing the second dummy gate to expose the portion of the second set of nanowires that serves as the channel region of the diode device within a second trench in the filler layer.

12. The method of claim 11 , wherein the first dummy gate and the second dummy gate comprise polysilicon.

13. The method of claim 11 , wherein the first dummy gate and the second dummy gate are removed using a wet etching process.

14. The method of claim 1 , wherein the step of selectively forming the conformal gate dielectric layer on the portion of each of the first set of nanowires that serves as the channel region of the transistor device comprises the steps of:
depositing the conformal gate dielectric layer on the portion of the first set of nanowires that serves as the channel region of the transistor device and on the portion of the second set of nanowires that serves as the channel region of the diode device; and
selectively removing the dielectric layer from the second set of nanowires that serves as the channel region of the diode device.

15. The method of claim 14 , further comprising the step of:
masking the conformal gate dielectric layer deposited on the portion of the first set of nanowires that serves as the channel region of the transistor device.

16. The method of claim 14 , wherein the dielectric layer is selectively removed from the second set of nanowires that serves as the channel region of the diode device using a wet etching process.

17. The method of claim 1 , further comprising the step of:
forming spacers on opposite sides of the first metal gate stack and on opposite sides of the second metal gate stack.

18. The method of claim 1 , wherein portions of the first set of nanowires extending out from the first metal gate stack and the first set of pads serve as source and drain regions of the transistor device, and wherein portions of the second set of nanowires extending out from the second metal gate stack and the second set of pads serve as source and drain regions of the diode device, the method further comprising the step of:
growing epitaxial silicon over the source and drain regions of the transistor device and over the source and drain regions of the diode device.

Assignees

• IBM

Inventors

• Chang Josephine B
• Lauer Isaac
• Lin Chung-Hsun
• Sleight Jeffrey W

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title