Split gate non-volatile memory cell with 3D finFET structure, and method of making same

Patent metadata

Field	Value
Publication number	US-9634018-B2
Application number	US-201615050309-A
Country	US
Kind code	B2
Filing date	Feb 22, 2016
Priority date	Mar 17, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

First claim

The invention claimed is:

1. A non-volatile memory cell comprising:
a semiconductor substrate of a first conductivity type having a fin shaped upper surface portion having a top surface and two side surfaces;
spaced apart first and second regions of a second conductivity type different than the first conductivity type in the fin shaped upper surface portion, with a channel region extending between the first region and the second region;
wherein the channel region has a first portion that includes a first portion of the top surface and first portions of the two side surfaces, and has a second portion that includes a second portion of the top surface and second portions of the two side surfaces,
a conductive floating gate that includes:
a first portion that extends along and is insulated from the first portion of the top surface,
a second portion that extends along and is insulated from the first portion of one of the two side surfaces, and
a third portion that extends along and is insulated from the first portion of the other of the two side surfaces;

a conductive control gate that includes:
a first portion that extends along and is insulated from the second portion of the top surface,
a second portion that extends along and is insulated from the second portion of one of the two side surfaces,
a third portion that extends along and is insulated from the second portion of the other of the two side surfaces,
a fourth portion that extends up and over and is insulated from at least some of the floating gate first portion,
a fifth portion that extends out and over and is insulated from at least some of the floating gate second portion, and
a sixth portion that extends out and over and is insulated from at least some of the floating gate third portion.

2. The non-volatile memory cell of claim 1 , wherein the floating gate includes a sloping upper surface that terminates in a sharp edge that faces and is insulated from the control gate.

3. The non-volatile memory cell of claim 1 , wherein the channel region first portion is adjacent to the first region, and the channel region second portion is adjacent to the second region.

4. The non-volatile memory cell of claim 3 , wherein the floating gate partially extends over the first region.

5. A non-volatile memory array comprising:
a semiconductor substrate of a first conductivity type having a plurality of parallel fin shaped upper surface portions extending in a first direction each having a top surface and two side surfaces;
a plurality of memory cells formed on each one of the fin shaped upper surface portions, wherein each memory cell includes:
spaced apart first and second regions of a second conductivity type different than the first conductivity type in the one fin shaped upper surface portion, with a channel region extending between the first region and the second region;
wherein the channel region has a first portion that includes a first portion of the top surface and first portions of the two side surfaces, and has a second portion that includes a second portion of the top surface and second portions of the two side surfaces,
a conductive floating gate that includes:
a first portion that extends along and is insulated from the first portion of the top surface,
a second portion that extends along and is insulated from the first portion of one of the two side surfaces, and
a third portion that extends along and is insulated from the first portion of the other of the two side surfaces;

a conductive control gate that includes:
a first portion that extends along and is insulated from the second portion of the top surface,
a second portion that extends along and is insulated from the second portion of one of the two side surfaces,
a third portion that extends along and is insulated from the second portion of the other of the two side surfaces,
a fourth portion that extends up and over and is insulated from at least some of the floating gate first portion,
a fifth portion that extends out and over and is insulated from at least some of the floating gate second portion, and
a sixth portion that extends out and over and is insulated from at least some of the floating gate third portion;

a plurality of control gate lines each extending in a second direction perpendicular to the first direction and electrically connected to one of the control gates for each of the fin shaped upper surface portions.

6. The non-volatile memory array of claim 5 , further comprising:
a plurality of parallel diffusion lines in the substrate extending in the second direction, wherein each diffusion line is electrically connected to two of the first regions in each of the fin shaped upper surface portions.

7. The non-volatile memory array of claim 5 , further comprising:
a plurality of contacts each extending from and electrically connected to two of the first regions; and
a plurality of source lines extending in the second direction and electrically connected to one of the plurality of contacts for each of the fin shaped upper surface portions.

8. The non-volatile memory array of claim 5 , wherein each of the floating gates includes a sloping upper surface that terminates in a sharp edge that faces and is insulated from one of the control gates.

9. The non-volatile memory array of claim 5 , wherein each of the channel region first portions is adjacent to one of the first regions, and each of the channel region second portions is adjacent to one of the second regions.

10. The non-volatile memory array of claim 9 , wherein each of the floating gates partially extends over one of the first regions.

Assignees

• Silicon Storage Tech Inc

Inventors

• Su Chien-Sheng
• Yang Jeng-Wei
• Wu Man-Tang
• Chen Chun-Ming
• Tran Hieu Van
• Do Nhan

Classifications

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H01L27/11551

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic