FinFET based flash memory cell

Patent metadata

Field	Value
Publication number	US-10032891-B2
Application number	US-201715498652-A
Country	US
Kind code	B2
Filing date	Apr 27, 2017
Priority date	Mar 21, 2016
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.

First claim

What is claimed:

1. A method of manufacturing a flash memory cell, comprising:
forming a plurality of semiconductor fins on a semiconductor substrate;
forming floating gates for a sub-set of said plurality of semiconductor fins;
forming a first insulating layer between said plurality of semiconductor fins;
recessing said first insulating layer to a height less than a height of said plurality of semiconductor fins;
forming sacrificial gates over said sub-set of said plurality of semiconductor fins;
forming a second insulating layer between said sacrificial gates;
removing said sacrificial gates;
forming recesses in said first insulating layer; and
forming sense gates and control gates in said recesses for said sub-set of said plurality of semiconductor fins.

2. The method of claim 1 , wherein said sense gates and said control gates are formed by forming a gate layer in said recesses, over said sub-set of said plurality of semiconductor fins and over said second insulating layer and polishing back the thus formed gate layer to a height level of said sub-set of said plurality of semiconductor fins.

3. The method of claim 1 , further comprising forming high-k dielectrics between said sense gates and said sub-set of said plurality of semiconductor fins.

4. The method of claim 1 , further comprising forming floating gates between said sub-set of said plurality of semiconductor fins and said control gates.

5. The method of claim 1 , further comprising forming a protection layer above said plurality of semiconductor fins after recessing said first insulating layer and before forming said sacrificial gates.

6. The method of claim 5 , further comprising removing said protection layer after removing said sacrificial gates.

7. The method of claim 1 , further comprising forming a first layer of insulating material over said plurality of semiconductor fins prior to forming said floating gates.

8. The method of claim 1 , further comprising forming a high-k dielectric layer in said recesses prior to forming said sense gates and said control gates.

9. The method of claim 1 , wherein forming said sense gates and said control gates comprises:
forming a metal layer to overfill said recesses; and
planarizing said metal layer and said second insulating layer to expose upper surfaces of said plurality of semiconductor fins, said sense gates, and said control gates.

10. The method of claim 9 , further comprising forming contacts above and in contact with said upper surfaces of said sense gates and said control gates.

11. A method of manufacturing a flash memory cell, comprising:
forming a first plurality of semiconductor fins on a semiconductor substrate;
forming floating gates for a sub-set of said first plurality of semiconductor fins on sidewall surfaces of said sub-set of said first plurality of semiconductor fins;
forming a first insulating layer between said first plurality of semiconductor fins;
recessing said first insulating layer to a height less than a height of said first plurality of semiconductor fins;
forming sacrificial gates over said sub-set of said first plurality of semiconductor fins;
forming a second insulating layer between said sacrificial gates;
removing said sacrificial gates to define first gate recesses on a first side of said sub-set of said first plurality of semiconductor fins and a second gate recesses on a second side of said sub-set of said first plurality of semiconductor fins proximate said floating gates;
extending said first and second gate recesses into said first insulating layer; and
forming sense gates in said first gate recesses and control gates in said second gate recesses.

12. The method of claim 11 , further comprising forming a protection layer above said first plurality of semiconductor fins after recessing said first insulating layer and before forming said sacrificial gates.

13. The method of claim 11 , further comprising forming a first layer of insulating material over said first plurality of semiconductor fins prior to forming said floating gates.

14. The method of claim 11 , further comprising forming a high-k dielectric layer in said first and second gate recesses prior to forming said sense gates and said control gates.

15. The method of claim 11 , wherein forming said sense gates and said control gates comprises:
forming a metal layer to overfill said first and second gate recesses; and
planarizing said metal layer and said second insulating layer to expose upper surfaces of said first plurality of semiconductor fins, said sense gates, and said control gates.

16. The method of claim 15 , further comprising forming contacts above and in contact with said upper surfaces of said sense gates and said control gates.

17. The method of claim 11 , wherein forming said floating gates comprises:
forming a floating gate material layer above said first plurality of semiconductor fins;
forming an angled mask layer across said first plurality of semiconductor fins;
implanting ions into portions of said floating gate material layer not covered by said angled mask layer to define implant regions; and
selectively removing said implant regions to define said floating gates.

18. The method of claim 11 , further comprising:
forming a second plurality of semiconductor fins on said semiconductor substrate;
forming said first insulating layer between said second plurality of semiconductor fins;
forming one of said sacrificial gates above said second plurality of semiconductor fins;
removing said sacrificial gate above said second plurality of sacrificial gates to define a third gate recess above said second plurality of semiconductor gates;
extending said third gate recess concurrently with extending said first and second gate recesses; and
forming a gate electrode in said third recess concurrently with forming said sense gates and said control gates.

19. The method of claim 18 , further comprising reducing a height of said second plurality of semiconductor fins relative to said height of said first plurality of semiconductor fins.

20. The method of claim 18 , wherein forming said gate electrode, said sense gates, and said control gates comprises forming a conductive layer in said first, second, and third gate recesses.

Assignees

• Globalfoundries Inc

Inventors

• Baars Peter
• Faul Juergen

Classifications

• H10P30/22

  using masks · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H01L27/11524

  Electricity · mapped topic

• H01L21/266

  Electricity · mapped topic