Forming interconnect structure using plasma treated metal hard mask

Patent metadata

Field	Value
Publication number	US-10312107-B2
Application number	US-201113228011-A
Country	US
Kind code	B2
Filing date	Sep 8, 2011
Priority date	Sep 8, 2011
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

First claim

What is claimed is:

1. A method comprising:
forming a metal hard mask over a low-k dielectric layer, wherein the step of forming the metal hard mask comprises:
depositing a first layer of the metal hard mask comprising horizontal grains and vertical grains;
performing a plasma treatment on the first layer of the metal hard mask, wherein the first layer of the metal hard mask has a first thickness, and wherein after the plasma treatment, the metal hard mask is substantially free from vertical grains;
depositing a second layer of the metal hard mask, wherein the second layer of the metal hard mask has a second thickness different from the first thickness of the first layer of the metal hard mask; and
performing a plasma treatment on the second layer of the metal hard mask;

patterning the metal hard mask to form an opening;
etching the low-k dielectric layer to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask;
forming a diffusion barrier layer in the trench;
filling a metallic material into the trench, wherein the metallic material is over the diffusion barrier layer, and the diffusion barrier layer and the metallic material comprise portions overlapping the metal hard mask; and
performing a chemical mechanical polish (CMP) to remove excess portions of the metallic material over the metal hard mask.

2. The method of claim 1 , wherein the step of forming the metal hard mask further comprises a plurality of deposition-treatment cycles, and wherein each of the deposition-treatment cycles comprises:
depositing a first additional layer of the metal hard mask;
performing a plasma treatment on the first additional layer of the metal hard mask; depositing a second additional layer of the metal hard mask; and
performing a plasma treatment on the second additional layer of the metal hard mask.

3. The method of claim 2 , wherein the additional layer and the layer are formed of a same material.

4. The method of claim 1 , wherein the low-k dielectric layer is over a substrate having a major surface, wherein the horizontal grains have slant angles smaller than 45 degrees with the major surface, and the vertical grains have slant angles greater than 45 degrees with the major surface.

5. The method of claim 1 , wherein the CMP is performed until the metal hard mask is fully removed.

6. The method of claim 1 , wherein the plasma treatment lasts between about 1 second and about 10 seconds, and wherein during the plasma treatment, a wafer comprising the metal hard mask and the low-k dielectric layer is at a temperature between about 200° C. and about 450° C.

7. The method of claim 1 , wherein the metal hard mask comprises a material selected from the group consisting essentially of boron nitride.

8. The method of claim 1 further comprising:
forming a via opening in the low-k dielectric layer, wherein the via opening is underlying the trench, and wherein a location and a size of the via opening is limited by the metal hard mask during the step of forming the via opening, wherein the diffusion barrier layer and the metallic material are also filled into the via opening.

9. A method comprising:
forming a low-k dielectric layer over a semiconductor substrate;
forming a metal hard mask over the low-k dielectric layer, wherein the metal hard mask comprises a plurality of sub-layers distinguishable from each other, with the plurality of sub-layers comprising boron nitride, wherein the forming the metal hard mask is performed at least in part with an atomic layer deposition, wherein a first sub-layer of the plurality of sub-layers of the metal hard mask is formed directly over the low-k dielectric layer prior to forming the remainder of the plurality of sub-layers of the metal hard mask, wherein the first sub-layer of the plurality of sub-layers of the metal hard mask has a first thickness, and wherein at least one of the plurality of sub-layers of the metal hard mask has a second thickness different from the first thickness of the first sub-layer of the plurality of sub-layers of the metal hard mask;
patterning the metal hard mask to form an opening in the metal hard mask;
etching the low-k dielectric layer to form a trench using the metal hard mask as an etching mask;
etching the low-k dielectric layer to form a via opening in the low-k dielectric layer; and
forming a metal line and a via in the trench and the via opening, respectively, wherein the forming the metal line and the via comprises:
filling a conductive material into the trench and the openings; and
performing a planarization to remove excess portions of the conductive material and the metal hard mask, with remaining portions of the conductive material forming the metal line and the via.

10. The method of claim 9 , wherein the step of forming the metal hard mask comprises a plurality of deposition-treatment cycles, and wherein each of the deposition-treatment cycles comprises:
depositing one of the plurality of sub-layers of the metal hard mask; and
bombarding the one of the plurality of sub-layers to convert vertical grains to horizontal grains.

11. The method of claim 10 , wherein in the bombarding, substantially all vertical grains in the one of the plurality of sub-layers are converted to horizontal grains.

12. The method of claim 10 , wherein the metal hard mask comprises grains, and a percentage of vertical grains to all grains is smaller than about 20 percent.

13. A method comprising:
forming a metal hard mask over a low-k dielectric layer, wherein the forming the metal hard mask comprises:
depositing a first sub layer of the metal hard mask comprising horizontal grains and vertical grains, wherein the first sub layer of the metal hard mask has a first thickness;
modifying directions of longitudinal axis of grains in the first sub layer of the metal hard mask, wherein substantially all vertical grains are converted to horizontal grains;
depositing a second sub layer of the metal hard mask comprising horizontal grains and vertical grains, wherein the second sub layer of the metal hard mask has a second thickness different from the first thickness of the first sub layer of the metal hard mask; and
modifying directions of longitudinal axis of grains in the second sub layer of the metal hard mask, wherein substantially all vertical grains are converted to horizontal grains;

patterning the metal hard mask to form an opening;
etching the dielectric layer to form a trench, wherein the etching is performed using the metal hard mask as an etching mask;
filling the trench with a conductive material, wherein the conductive material comprises:
a first portion in the trench;
a second portion extending into the metal hard mask; and
a third portion higher than the metal hard mask; and

performing a planarization to remove the metal hard mask and the second portion and the third portion of the conductive material.

14. The method of claim 13 , wherein the metal hard mask comprises boron nitride.

15. The method of claim 13 , wherein the modifying directions comprises bombarding the metal hard mask.

16. The method of claim 13 , wherein the modifying directions is performed after the depositing.

17. The method of claim 13 further comprising a plurality of deposition-treatment cycles to increase a thickness of the metal hard mask, wherein each of the deposition-treatment cycles comprises:
depositing an additional sub layer of the metal hard mask; and
performing a plasma treatment on the additional sub layer of the metal hard mask.

Assignees

• Ko Chung Chi
• Chou Chia Cheng
• Pan Shing Chyang
• Lin Keng Chu
• Jeng Shwang Ming
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ko Chung-Chi
• Chou Chia-Cheng
• Pan Shing-Chyang
• Lin Keng-Chu
• Jeng Shwang-Ming

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H01L21/76811

  Electricity · mapped topic