Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10304807-B2
Application number	US-201815951571-A
Country	US
Kind code	B2
Filing date	Apr 12, 2018
Priority date	Sep 12, 2016
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the first semiconductor chip, and the connection pads of the second semiconductor chip are electrically connected to the redistribution layer of the first interconnection member by wires.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a first interconnection member having a through-hole;
a first semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
a first encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the first semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the first semiconductor chip;
a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and
a second encapsulant encapsulating at least portions of the second semiconductor chip,
wherein the first interconnection member include three or more redistribution layers separate from each other by two or more insulating layers and electrically connected to the connection pads of the first semiconductor chip at least through vias respectively penetrating the two or more insulating layers,
the second interconnection member include a redistribution layer electrically connected to the connection pads of the first semiconductor chip, and
the connection pads of the second semiconductor chip are electrically connected to an uppermost layer among the three or more the redistribution layers of the first interconnection member by wires.

2. The fan-out semiconductor package of claim 1 , wherein the first encapsulant has openings exposing portions the uppermost redistribution layer of the first interconnection member which the wires are bonded to.

3. The fan-out semiconductor package of claim 1 , wherein the first semiconductor chip includes a processor chip, and
the second semiconductor chip includes a memory chip.

4. The fan-out semiconductor package of claim 1 , wherein a number of the three of more of the redistribution layers of the first interconnection member is three and a number of the two of more of the insulating layers of the first interconnection member is two, and
the first interconnection member includes a first insulating layer, a first redistribution layer contacting the second interconnection member and embedded in a first surface of the first insulating layer, a second redistribution layer disposed on a second surface of the first insulating layer opposing the first surface of the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the second redistribution layer, and a third redistribution layer as the uppermost redistribution layer disposed on the second insulating layer.

5. The fan-out semiconductor package of claim 4 , wherein a distance between the redistribution layer of the second interconnection member and the first redistribution layer is greater than that between the redistribution layer of the second interconnection member and the connection pad of the first semiconductor chip.

6. The fan-out semiconductor package of claim 4 , wherein the first redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member.

7. The fan-out semiconductor package of claim 4 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the first semiconductor chip.

8. The fan-out semiconductor package of claim 1 , wherein a number of the three of more of the redistribution layers of the first interconnection member is four and a number of the two of more of the insulating layers of the first interconnection member is three, and
the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on both surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, a third redistribution layer disposed on the second insulating layer, a third insulating layer disposed on the first insulating layer and covering the second redistribution layer, and a fourth redistribution layer as the uppermost redistribution layer disposed on the third insulating layer.

9. The fan-out semiconductor package of claim 8 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.

10. The fan-out semiconductor package of claim 8 , wherein the third redistribution layer has a thickness greater than that of the redistribution layer of the second interconnection member.

11. The fan-out semiconductor package of claim 8 , wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the first semiconductor chip.

12. A fan-out semiconductor package comprising:
a first interconnection member having a through-hole;
a first semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
a first encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the first semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the first semiconductor chip;
a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon;
a second encapsulant encapsulating at least portions of the second semiconductor chip;
a backside redistribution layer disposed on the first encapsulant; and
a backside via penetrating through the first encapsulant and electrically connecting the backside redistribution layer and the redistribution layer of the first interconnection member to each other,
wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the first semiconductor chip, and
the backside redistribution layer includes wire pads connected to the connection pads of the second semiconductor chip by wires and wiring patterns redistributing the connection pads of the second semiconductor chip.

13. The fan-out semiconductor package of claim 12 , further comprising a passivation layer disposed on the first encapsulant and having openings exposing portions of the backside redistribution layer which the wires are bonded to,
wherein the second semiconductor chip is disposed on the passivation layer.

14. The fan-out semiconductor package of claim 12 , wherein the first semiconductor chip includes a processor chip, and
the second semiconductor chip includes a memory chip.

15. The fan-out semiconductor package of claim 12 , wherein the redistribution layers of the first interconnection member includes first and second redistribution layers,
the first interconnection member further includes a first insulating layer,
the first redistribution layer contacts the second interconnection member and is embedded in a first surface of the first insulating layer, and
the second redistribution layer is disposed on a second surface of the first insulating layer opposing the first surface of the first insulating layer.

16. The fan-out semiconductor package of claim 15 , wherein a lower surface of the first insulating layer has a step with respect to a lower surface of the first redistribution layer.

17. The fan-out semiconductor package

Assignees

• Samsung Electro Mech

Inventors

• Park Dae Hyun
• Jo Eun Jung
• Jeong Sung Won
• Kim Han
• Han Mi Ja

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W90/00 Primary

  Package configurations · CPC title