Wafer reinforcement to reduce wafer curvature

Patent metadata

Field	Value
Publication number	US-10304783-B2
Application number	US-201715707504-A
Country	US
Kind code	B2
Filing date	Sep 18, 2017
Priority date	Oct 2, 2015
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

First claim

What is claimed is:

1. A wafer comprising:
a silicon on insulator (SOI) layer formed directly upon a buried insulating layer, the buried insulating layer formed directly upon a substrate;
a filled deep trench associated with a microdevice within the wafer, wherein the filled deep trench is filled with a first filler comprised of a trench material, the first filler comprising an upper surface coplanar with the SOI layer upper surface;
filled dual reinforcement trenches separated by dielectric material within the wafer, each filled dual reinforcement trench comprising:
a liner comprised of the trench material directly upon one or more sidewalls of each of the dual reinforcement trenches and directly upon one or more lower surfaces of each of the dual reinforcement trenches, the liner comprising an upper surface coplanar with the SOI upper surface; and
a second filler comprised of a reinforcing material directly upon the trench material, the second filler comprising an upper surface coplanar with the SOI upper surface;

wherein the deep trench and filled dual reinforcing trenches extend through the SOI layer, through the buried insulating layer, and partially through the substrate;
a first conductive contact directly upon at least the first filler; and
a second conductive contact directly upon at least the liner of one of the dual reinforcing trenches.

2. The wafer of claim 1 , wherein the reinforcing material has a material strength measurement greater than the trench material.

3. The wafer of claim 1 , wherein each dual reinforcement trench width is greater than the deep trench width.

4. The wafer of claim 1 , wherein each dual reinforcement trench depth is greater than the deep trench depth.

5. The wafer of claim 1 , wherein the filled dual reinforcement trenches are included in a global reinforcement trench array throughout the wafer.

6. The wafer of claim 1 , wherein the filled dual reinforcement trenches are included in a perimeter region at the edge of the wafer.

7. The wafer of claim 1 , wherein the filled dual reinforcement trenches are included the wafer kerf.

Assignees

• IBM

Inventors

• Kaltalioglu Erdem
• Kim Andrew T
• Pei Chengwen
• Wang Ping-Chuan

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title