Fine delay structure with programmable delay ranges

Patent metadata

Field	Value
Publication number	US-10291217-B2
Application number	US-201715456985-A
Country	US
Kind code	B2
Filing date	Mar 13, 2017
Priority date	Jun 18, 2015
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.

First claim

What is claimed is:

1. A method for delaying a signal comprising:
receiving a signal at a first node in a circuit;
passing the signal through a first inverter connected to the first node and a second node;
receiving the signal at a variable resistive element connected to the second node and a third node;
changing an amplitude of the signal with a first switch connected to the second node;
receiving the signal at a first capacitive element connected in series with the first switch and the third node and arranged in parallel and connected with the first node and the second node;
changing a state of a second switch connected to the second node;
receiving the signal at a second capacitive element connected in series with the second switch and the third node and arranged in parallel and connected with the first node and the second node; and
inverting a delayed signal via a second inverter connected to the third node and a fourth node.

2. The method of claim 1 , further comprising controlling, via a controller operatively connected to the first switch and the second switch, a state of the first switch and a state of the second switch.

3. The method of claim 2 , further comprising controlling, via the controller, the state of the first switch and the state of the second switch independently.

4. The method of claim 2 , further comprising changing a total capacitance of the circuit via the state of the first switch.

5. The method of claim 2 , further comprising controlling a switching device connected to the variable resistive element via the controller.

6. The method of claim 5 , further comprising controlling a voltage applied to the variable resistive element with the switching device.

7. The method of claim 1 , wherein the variable resistive element includes a field effect transistor device.

8. The method of claim 1 , wherein a capacitance of the first capacitive element is dissimilar from a capacitance of the second capacitive element.

9. The method of claim 1 , wherein a capacitance of the first capacitive element is equal to a capacitance of the second capacitive element.

Assignees

• IBM

Inventors

• Prasad Mangal
• Tiner Marshall D
• Tran Hung H
• Yuan Xiaobin

Classifications

• H03K17/284

  in field effect transistor switches · CPC title

• H03K2005/00071

  by adding capacitance as a load · CPC title

• H03K5/14 Primary

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03K5/131 Primary

  Digitally controlled · CPC title