Fine delay structure with programmable delay ranges

Patent metadata

Field	Value
Publication number	US-9712144-B2
Application number	US-201514844197-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	Jun 18, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.

First claim

What is claimed is:

1. A system comprising:
a coarse signal delay portion operative to receive a signal and output a coarse delay signal; and
a fine signal delay portion comprising:
a first node connected to an output node of the coarse signal delay portion;
a first inverter connected to the first node and a second node;
a variable resistive element connected to the second node and a third node, wherein the variable resistive element includes a field effect transistor device;
a first switch connected to the second node;
a first capacitive element connected in series with the first switch and the third node and arranged in parallel and connected with the first node and the second node;
a second switch connected to the second node;
a second capacitive element connected in series with the second switch and the third node and arranged in parallel and connected with the first node and the second node; and
a second inverter connected to the third node and a fourth node.

2. The system of claim 1 , further comprising a controller connected to the first switch and the second switch, the controller operative to control a state of the first switch and a state of the second switch.

3. The system of claim 2 , wherein the controller is operative to control the state of the first switch and the state of the second switch independently.

4. The system of claim 2 , wherein the state of the first switch is operative to change a total capacitance of the circuit.

5. The system of claim 1 , wherein the switching device is operative to control a voltage applied to the variable resistive element.

6. The system of claim 1 , wherein a capacitance of the first capacitive element is dissimilar from a capacitance of the second capacitive element.

7. The system of claim 1 , wherein a capacitance of the first capacitive element is equal to a capacitance of the second capacitive element.

Assignees

• IBM

Inventors

• Prasad Mangal
• Tiner Marshall D
• Tran Hung H
• Yuan Xiaobin

Classifications

• H03K5/14 Primary

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03K5/131 Primary

  Digitally controlled · CPC title

• H03K2005/00071

  by adding capacitance as a load · CPC title

• H03K17/284

  in field effect transistor switches · CPC title