Programmable delay circuit

Patent metadata

Field	Value
Publication number	US-9407247-B2
Application number	US-201414520743-A
Country	US
Kind code	B2
Filing date	Oct 22, 2014
Priority date	Apr 9, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A computing circuit that includes clocked circuitry, a controller, and a clock generator. The clocked circuitry is configured to receive data and to perform data manipulation on the data based on a first clock signal. The controller is configured to control the transmission of the data to the clocked circuitry. The clock generator is configured to receive as inputs a second clock signal and a delay control signal from the controller, and to delay the second clock signal to generate the first clock signal. The clock generator includes a main delay component configured to receive the second clock signal and to output the first clock signal. The clock generator also includes a switchable delay component connected in parallel with the main delay component, where the switchable delay component is configured to receive as an input the delay control signal from the controller.

First claim

What is claimed is:

1. A computing circuit, comprising:
clocked circuitry configured to receive data and perform data manipulation on the data based on a first clock signal;
a controller configured to control the transmission of the data to the clocked circuitry; and
a clock generator configured to receive as inputs a second clock signal and a delay control signal from the controller, and configured to delay the second clock signal to generate the first clock signal, the delay control signal including a first delay control signal and a second delay control signal, the clock generator comprising:
a main delay component configured to receive the second clock signal and output the first clock signal; and
a switchable delay component connected in parallel with the main delay component, the switchable delay component including:
a first switchable inverter connected in parallel with the main delay component, the first switchable inverter turned on and off by the first delay control signal, wherein the first switchable inverter includes a first set of switchable inverters connected in series with each other and turned on and off by the same first delay control signal; and
a second switchable inverter connected in parallel with the first switchable inverter and the main delay component, the second switchable inverter turned on and off by the second delay control signal, wherein the second switchable inverter includes a second set of switchable inverters connected in series with each other and turned on and off by the same second delay control signal,
wherein the second set of switchable inverters are connected in parallel with the first set of switchable inverters, and
the switchable delay component is configured to receive as an input the delay control signal from the controller.

2. The computing circuit of claim 1 , wherein the switchable delay component corresponds to a delay that is less than the main delay component.

3. The computing circuit of claim 1 , wherein the switchable delay component corresponds to a delay that is more than the main delay component.

4. The computing circuit of claim 1 , wherein the switchable delay component is configured to reduce a delay of the first clock signal with respect to the second clock signal based on the switchable delay component being turned on.

5. The computing circuit of claim 1 , wherein the main delay component includes an even number of main inverters connected in series, and
the switchable delay component includes an even number of switchable inverters connected in series with each other.

6. The computing circuit of claim 5 , wherein the even number of main inverters includes a first main inverter and a second main inverter, and the even number of switchable inverters includes a first switchable inverter and a second switchable inverter, and
the first switchable inverter is connected in parallel with the first main inverter and the second switchable inverter is connected in parallel with the second main inverter.

7. The computing circuit of claim 5 , wherein each of the switchable inverters connected in series with each other is turned on and off by the same delay control signal.

8. The computing circuit of claim 1 , wherein the delay control signal includes a delay control byte, and
the at least one switchable inverter includes eight sets of switchable inverters, including the first and second sets of switchable inverters, each of the eight sets of switchable inverters turned on and off by a different bit of the delay control byte.

Assignees

• IBM

Inventors

• Drake Alan J
• Owczarczyk Pawel
• Tiner Marshall D
• Yuan Xiaobin

Classifications

• H03K5/133 Primary

  using a chain of active delay devices · CPC title

• H03K5/131

  Digitally controlled · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title

• H03K2005/0015

  Layout of the delay element · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title