FinFET devices having a material formed on reduced source/drain region

Patent metadata

Field	Value
Publication number	US-10290724-B2
Application number	US-201715498272-A
Country	US
Kind code	B2
Filing date	Apr 26, 2017
Priority date	Sep 26, 2014
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region. The device also has a gate structure overlying the fin structure. The source region includes an inner portion of the first semiconductor material and an outer portion of a second semiconductor material overlying a top surface and side surfaces of the inner portion. The drain region includes an inner portion of the first semiconductor material and an outer portion of the second semiconductor material overlying a top surface and side surfaces of the inner portion.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a fin structure of a first semiconductor material on a substrate;
a gate structure overlying and across the fin structure;
a channel region comprising a first portion of the fin structure under the gate structure, the first portion having a first width measured between opposite sidewalls of the first portion;
a source region comprising a second portion of the fin structure not under the gate structure, the second portion having a second width measured between opposite sidewalls of the second portion, the second width being smaller than the first width; and
a drain region comprising a third portion of the fin structure not under the gate structure, the third portion having a third width measured between opposite sidewalls of the third portion, the third width being smaller than the the first width;
wherein the source region further comprises a layer of a second semiconductor material overlying a top surface, a first and a second side surfaces, and an end surface of the second portion of the fin structure;
wherein the drain region further comprises a layer of the second semiconductor material overlying a top surface, a first and a second side surfaces, and an end surface of the third portion of the fin structure.

2. The device of claim 1 , wherein a top surface of the source region is higher than a top surface of the channel region.

3. The device of claim 1 , wherein the first semiconductor material comprises a silicon (Si) material, and the second semiconductor material comprises a silicon germanium (SiGe) material.

4. The device of claim 1 , wherein the first semiconductor material comprises a silicon (Si) material, and the second semiconductor material comprises a silicon carbide (SiC) material.

5. A semiconductor device, comprising:
a fin structure of a first semiconductor material on a substrate, the fin structure having a source region, a drain region, and a channel region between the source region and the drain region;
a gate structure overlying the channel region having a first width;
wherein the source region includes an inner portion of the first semiconductor material having a second width and an outer portion of a second semiconductor material overlying a top surface and side surfaces of the inner portion;
wherein the drain region includes an inner portion of the first semiconductor material having a third width and an outer portion of the second semiconductor material overlying a top surface and side surfaces of the inner portion,
wherein the first width measured between opposite sidewalls of the channel region is greater than the second width measured between opposite sidewalls of the source region, and the first width is greater than the third width measured between opposite sidewalls of the source region.

6. The device of claim 5 , wherein a height of the outer portion of the source region is higher than a top surface of the channel region.

7. The device of claim 5 , wherein a height of the outer portion of the drain region is higher than a top surface of the channel region.

8. The device of claim 5 , wherein the first semiconductor material comprises a silicon (Si) material, and the second semiconductor material comprises a silicon germanium (SiGe) material.

9. The device of claim 8 , wherein the first semiconductor material comprises a silicon (Si) material, and the second semiconductor material comprises a silicon carbide (SiC) material.

10. A semiconductor device, comprising:
a substrate;
a fin structure of a first semiconductor material on the substrate, the fin structure comprising a source region, a drain region, and a channel region;
wherein a first width measured between opposite sidewalls of the channel region is greater than a second width measured between opposite sidewalls of the source region.

11. The semiconductor device of claim 10 , wherein the drain region has a third width measured between opposite sidewalls of the drain region that is smaller than the first width.

12. The semiconductor device of claim 11 , wherein the fin structure further comprises a second semiconductor material overlying a first top surface and first opposite side surfaces of the source region, a second top surface and second opposite side surfaces of the drain region, and opposite distal end surfaces of the fin structure.

13. The semiconductor device of claim 12 , wherein:
the first semiconductor material comprises a silicon material; and
the second semiconductor material comprises a silicon germanium material.

14. The semiconductor device of claim 12 , wherein:
the first semiconductor material comprises a silicon material; and
the second semiconductor material comprises a silicon carbide material.

15. The semiconductor device of claim 12 , wherein the second semiconductor material has an upper surface higher than an upper surface of the channel region.

16. The semiconductor device of claim 12 , wherein the second and third widths each are in the range between 1/10 and 9/10 of the first width.

17. The semiconductor device of claim 12 , wherein the second and third widths each are in the range between ½ and ¾ of the first width.

18. The semiconductor device of claim 12 , wherein the second and third widths each are in the range between ¼ and ½ of the first width.

19. The semiconductor device of claim 12 , wherein the second semiconductor material completely surrounds the source region and the drain region.

20. The semiconductor device of claim 12 , wherein the second semiconductor material is an epitaxially grown semiconductor material.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Xie Xinyun

Classifications

• H10P50/642

  Chemical etching · CPC title

• H01L21/823814

  Electricity · mapped topic

• H01L21/30604

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L29/66795 Primary

  Electricity · mapped topic