FinFET device having a material formed on reduced source/drain region and method of forming the same

Patent metadata

Field	Value
Publication number	US-9673325-B2
Application number	US-201514842773-A
Country	US
Kind code	B2
Filing date	Sep 1, 2015
Priority date	Sep 26, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region. The device also has a gate structure overlying the fin structure. The source region includes an inner portion of the first semiconductor material and an outer portion of a second semiconductor material overlying a top surface and side surfaces of the inner portion. The drain region includes an inner portion of the first semiconductor material and an outer portion of the second semiconductor material overlying a top surface and side surfaces of the inner portion.

First claim

What is claimed is:

1. A method for forming a semiconductor device, comprising:
forming a fin structure of a first semiconductor material on a substrate, the fin structure comprising a source region, a drain region, and a channel region between the source and drain regions, the source and drain regions each having a first height, a first width, and a first length;
forming a gate structure overlying the channel region;
removing an outer portion of the first semiconductor material from a top surface, from first and second side surfaces opposite to each other, and from an end surface of the source region or the drain region to form a reduced source region or a reduced drain region having a second height smaller than the first height, a second width smaller than the first width, and a second length smaller than the first length; and
forming a layer of a second semiconductor material on the top surface, the first and second side surfaces, and the end surface of the reduced source region or the reduced drain region.

2. The method of claim 1 , wherein removing a surface portion of the first semiconductor material comprises using a wet etching process.

3. The method of claim 2 , wherein the first semiconductor material is a silicon material, and the wet etching process comprises using a hydrofluoric acid (HF) based etching solution.

4. The method of claim 2 , wherein the wet etching process comprises using a mixture of nitric acid and hydrofluoric acid.

5. The method of claim 1 , wherein the second width of the reduced source region is in a range of from one half to three quarters of the width of the source region of the fin structure.

6. The method of claim 1 , wherein the second width of the reduced source region is in a range of from one quarter to one half of the width of the source region of the fin structure.

7. The method of claim 1 , wherein forming a layer of a second semiconductor material comprises using an epitaxial growth process.

8. The method of claim 1 , wherein the first semiconductor material is a silicon material, and the second semiconductor material comprises a silicon germanium (SiGe) material.

9. The method of claim 1 , wherein the first semiconductor material is a silicon material, and the second semiconductor material comprises a silicon carbide (SiC) material.

10. The method of claim 1 , wherein the first semiconductor material is a silicon material, and the second semiconductor material comprises a silicon material.

11. The method of claim 1 , wherein forming a fin structure comprises:
providing a substrate of a first semiconductor material; and
patterning and etching a surface portion of the substrate to form a fin structure.

12. The method of claim 11 , wherein forming a gate structure comprises:
forming a dielectric layer and a gate material layer over the fin structure; and
patterning and etching the dielectric layer and the gate material layer to form the gate structure.

13. The method of claim 1 , wherein the layer of the second semiconductor material has a top surface higher than a top surface of the channel region.

14. The method of claim 1 , wherein the layer of the second semiconductor material completely surrounds the reduced source region or the reduced drain region.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Xie Xinyun

Classifications

• H10P50/642

  Chemical etching · CPC title

• H01L29/7851

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic

• H01L21/30604

  Electricity · mapped topic

• H01L29/7848 Primary

  Electricity · mapped topic