Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10290720-B2
Application number	US-201715642400-A
Country	US
Kind code	B2
Filing date	Jul 6, 2017
Priority date	Dec 28, 2012
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first oxide layer over and in contact with an insulating surface;
a second oxide layer over and in contact with the first oxide layer;
a third oxide layer over and in contact with the second oxide layer;
an insulating layer over and in contact with the third oxide layer; and
a gate electrode over and in contact with the insulating layer,
wherein each of the first oxide layer, the second oxide layer and the third oxide layer contains indium, gallium and zinc,
wherein a thickness of the second oxide layer is larger than a thickness of the first oxide layer; and
wherein each of the first oxide layer and the third oxide layer has an atomic ratio of zinc larger than an atomic ratio of indium, and an atomic ratio of gallium larger than the atomic ratio of zinc.

2. The semiconductor device according to claim 1 , wherein the first oxide layer has a same atomic ratio of indium, gallium and zinc as the third oxide layer.

3. The semiconductor device according to claim 1 , further comprising a source electrode and a drain electrode interposed between a portion of the second oxide layer and a portion of the third oxide layer.

4. The semiconductor device according to claim 1 , wherein the gate electrode is stacked layers, and one of the stacked layers includes at least one selected from an alloy of titanium and cobalt, an alloy of titanium and manganese, and an alloy of titanium and iron.

5. A semiconductor device comprising:
a first oxide layer over and in contact with an insulating surface;
a second oxide layer over and in contact with the first oxide layer;
a third oxide layer over and in contact with the second oxide layer;
an insulating layer over and in contact with the third oxide layer; and
a gate electrode over and in contact with the insulating layer,
wherein each of the first oxide layer, the second oxide layer and the third oxide layer contains indium, gallium and zinc,
wherein each of the first oxide layer and the third oxide layer has an atomic ratio of zinc larger than an atomic ratio of indium, and an atomic ratio of gallium larger than the atomic ratio of zinc, and
wherein the second oxide layer has an atomic ratio of indium larger than an atomic ratio of gallium and an atomic ratio of zinc.

6. The semiconductor device according to claim 5 , wherein the first oxide layer has a same atomic ratio of indium, gallium and zinc as the third oxide layer.

7. The semiconductor device according to claim 5 , further comprising a source electrode and a drain electrode interposed between a portion of the second oxide layer and a portion of the third oxide layer.

8. The semiconductor device according to claim 5 , wherein the gate electrode is stacked layers, and one of the stacked layers includes at least one selected from an alloy of titanium and cobalt, an alloy of titanium and manganese, and an alloy of titanium and iron.

9. A semiconductor device comprising:
a first oxide layer comprising In, Ga and Zn;
a second oxide layer over and in contact with the first oxide layer, the second oxide layer being formed by an oxide target (In:Ga:Zn=1:6:4); and
a gate electrode that overlaps with the first oxide layer and the second oxide layer.

10. The semiconductor device according to claim 9 , wherein the gate electrode is located over the second oxide layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Suzawa Hideomi
• Fujiki Hiroshi
• Godo Hiromichi
• Yamane Yasumasa

Classifications

• H01L27/1225

  Electricity · mapped topic

• H01L29/45

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic

• H01L29/4908 Primary

  Electricity · mapped topic

• H01L29/24

  Electricity · mapped topic