Method for manufacturing transistor

Patent metadata

Field	Value
Publication number	US-2017194465-A1
Application number	US-201715461767-A
Country	US
Kind code	A1
Filing date	Mar 17, 2017
Priority date	Dec 19, 2008
Publication date	Jul 6, 2017
Grant date	—

Abstract

A hydrogen barrier layer is selectively provided over an oxide semiconductor layer including hydrogen and hydrogen is selectively desorbed from a given region in the oxide semiconductor layer by conducting oxidation treatment, so that regions with different conductivities are formed in the oxide semiconductor layer. After that, a channel formation region, a source region, and a drain region can be formed with the use of the regions with different conductivities formed in the oxide semiconductor layer.

First claim

1 . A method for manufacturing a semiconductor device comprising the steps of:
forming an electrode over a substrate; forming an insulating layer over the electrode; forming an oxide semiconductor layer over the insulating layer; forming a layer selectively so as to leave a part of the layer overlapping with a second region of the oxide semiconductor layer, and so as to expose a first region of the oxide semiconductor layer; and performing an oxidizing treatment to the oxide semiconductor layer, wherein the first region includes hydrogen at a lower concentration than the second region, and wherein the electrode overlaps with the first region of the oxide semiconductor.

2 . The method for manufacturing a semiconductor device according to claim 1 , wherein the layer comprises a material selected from the group consisting of a silicon nitride, a silicon nitride oxide, a silicon oxide, a silicon oxynitride, an aluminum oxide, an aluminum nitride, an aluminum oxynitride, a titanium oxide, a tantalum oxide, a titanium nitride and a tantalum nitride.

3 . The method for manufacturing a semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium.

4 . The method for manufacturing a semiconductor device according to claim 1 , wherein concentration gradient of hydrogen is formed between the first region and the second region.

5 . The method for manufacturing a semiconductor device according to claim 1 , wherein the layer is a hydrogen barrier layer.

6 . The method for manufacturing a semiconductor device according to claim 1 , wherein a concentration of hydrogen included in the first region of the oxide semiconductor layer and a concentration of hydrogen included in the second region of the oxide semiconductor layer are measured by secondary ion mass spectrometry.

7 . The method for manufacturing a semiconductor device according to claim 1 , wherein a concentration of hydrogen included in the first region of the oxide semiconductor layer is greater than or equal to 1×10 16 atoms/cm 3 and less than or equal to 1×10 21 atoms/cm 3 .

Assignees

• Semiconductor Energy Lab

Inventors

• Sakata Junichiro

Classifications

• H10P14/3426

  Oxides · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/38

  characterised by treatments done after the formation of the materials · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title