Power device integration on a common substrate

Patent metadata

Field	Value
Publication number	US-10290703-B2
Application number	US-201715808029-A
Country	US
Kind code	B2
Filing date	Nov 9, 2017
Priority date	Jul 31, 2012
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

First claim

What is claimed is:

1. A semiconductor structure comprising at least one metal-oxide-semiconductor field-effect transistor (MOSFET) power device, the semiconductor structure comprising:
an active region;
a buried well having a first conductivity type formed in the active region;
a source region having a second conductivity type formed in the active region proximate an upper surface of the active region, the source region being electrically connected to the buried well;
a drain region having the second conductivity type formed in the active region proximate the upper surface of the active region and spaced laterally from the source region;
a body region having the first conductivity type formed in the active region between the source region and the drain region on at least a portion of the buried well;
a gate formed above the active region proximate the upper surface of the active region, wherein the gate is electrically isolated from the active region by a gate insulating layer;
a drain terminal formed on the upper surface of the active region and electrically connected to the drain region;
a source terminal electrically connected to the source region;
a gate terminal electrically connected to the gate; and
a shielding structure formed proximate the upper surface of the active region between the gate and the drain region, wherein the shielding structure comprises a field plate configured to control an electric field distribution along a top oxide interface away from an edge of the gate nearest the drain terminal;
wherein the buried well has a first end below the source terminal and a second end that extends partially below the drain region, the second end being laterally spaced from the drain terminal between the drain terminal and the body region; and
wherein the buried well is configured, in conjunction with the drain region, to form a clamping diode operative to position a breakdown avalanche region between the buried well and the drain terminal, and a breakdown voltage of the MOSFET power device is a function of one or more characteristics of the buried well.

2. The semiconductor structure of claim 1 , wherein:
the shielding structure overlaps at least a portion of the gate and is formed as an extension of a conductive layer contacting the source terminal.

3. The semiconductor structure of claim 1 , wherein:
the field plate comprises a stepped extension of the shielding structure formed proximate the drain terminal.

4. The semiconductor structure of claim 1 , further comprising:
an electrical connection between the source region and the body region;
wherein the electrical connection is a silicide layer lining a source contact trench; and
wherein the source contact trench extends through the source region into the body region.

5. The semiconductor structure of claim 1 , further comprising:
control circuitry integrated with the MOSFET power device on a common substrate, the control circuitry being configured to selectively control an operation of the MOSFET power device.

6. The semiconductor structure of claim 1 , further comprising:
a plurality of gate trench structures extending vertically from the upper surface of the active region into the buried well;
wherein each of the gate trench structures includes sidewalls and a bottom wall having an insulating material formed thereon;
wherein each of the gate trench structures is filled with a conductive material;
wherein the gate trench structures are electrically connected to the gate;
wherein a voltage applied to the gate is operative to modulate a conduction current which flows between the gate trench structures through the active region; and
wherein an amplitude of the conduction current is controlled as a function of the voltage.

Assignees

• Silanna Asia Pte Ltd

Inventors

• Korec Jacek
• Yang Boyi

Classifications

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title