Transistor package with three-terminal clip

Patent metadata

Field	Value
Publication number	US-10290567-B2
Application number	US-201715694086-A
Country	US
Kind code	B2
Filing date	Sep 1, 2017
Priority date	Sep 1, 2017
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A package which comprises an electrically conductive chip carrier, a first chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, a second chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, wherein the first chip and the second chip are connected to form a half bridge having inlet terminals and an outlet terminal, and a clip having three connection sections connecting the second connection terminal of the first chip with the first connection terminal of the second chip and with the outlet terminal of the half bridge.

First claim

What is claimed is:

1. A package, comprising:
an electrically conductive chip carrier;
a first chip with an integrated transistor and comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal;
a second chip with an integrated transistor and comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, wherein the first chip and the second chip are connected to form a half bridge having inlet terminals and an outlet terminal;
a clip having three connection sections connecting the second connection terminal of the first chip with the first connection terminal of the second chip and with the outlet terminal of the half bridge;
wherein the three connection sections of the clip are arranged at different height levels, in particular—at three different height levels.

2. The package according to claim 1 , wherein the three connection sections of the clip comprise a curved plate portion and a web portion extending from the curved plate portion, in particular substantially perpendicular from the curved plate portion.

3. The package according to claim 2 , wherein the curved plate portion comprises two planar subportions at different height levels connected by a slanted intermediate subportion.

4. The package according to claim 2 , wherein the web portion extends up to a lowermost height level of the clip.

5. The package according to claim 2 , wherein the curved plate portion is attached to a connection lead of the chip carrier and is attached to the first connection terminal of the second transistor chip.

6. The package according to claim 2 , wherein the web portion is attached to a leadframe body of the chip carrier on which leadframe body the first transistor chip is mounted.

7. The package according to claim 1 , comprising a further clip connecting the first connection terminal of the first chip with the chip carrier, in particular being at an electric reference potential, more particularly ground potential.

8. The package according to claim 1 , wherein at least one of the first chip and the second chip is configured for operation with a vertical current flow.

9. The package according to claim 1 , wherein the first chip is configured as a low-side switch and the second chip is configured as a high-side switch.

10. The package according to claim 1 , comprising a control chip connected to the control terminal of the first chip and to the control terminal of the second chip and being configured for controlling operation of the first chip and the second chip.

11. The package according to claim 10 , wherein the control chip is mounted on one of the group consisting of the first chip, the second chip, and a leadframe body of the chip carrier.

12. The package according to claim 1 , wherein the control terminals are arranged facing away from the chip carrier.

13. The package according to claim 1 , wherein two of the connection terminals, in particular the two first connection terminals, are arranged facing away from the chip carrier and the other two of the connection terminals, in particular the two second connection terminals, are arranged facing the chip carrier.

14. The package according to claim 1 , comprising an encapsulant, in particular a mold compound, partially encapsulating the chip carrier, and at least partially encapsulating the first chip and the second chip.

15. The package according to claim 1 , comprising one of the following features:
the first chip and the second chip have the same shape and dimension;
the first chip and the second chip have at least one of different shapes and different dimensions.

16. The package according to claim 1 , wherein the chip carrier comprises at least one of the group consisting of a leadframe, a Direct Copper Bonding substrate, and a Direct Aluminum Bonding substrate.

17. A package, comprising:
a leadframe-type chip carrier comprising connection leads and leadframe bodies;
a first chip with a field effect transistor and being arranged on one of the leadframe bodies;
a second chip with a field effect transistor and being arranged on another one of the leadframe bodies;
a clip having three connection sections contacting a surface of one of the chips, part of the connection leads and one of the leadframe bodies.

18. The package according to claim 17 , wherein the first chip and the second chip are connected to form a half bridge.

19. The package according to claim 17 , wherein source terminals and gate terminals of the first chip and of the second chip are facing away from the chip carrier, and drain terminals of the first chip and of the second chip are facing the chip carrier.

Assignees

• Infineon Technologies Ag

Inventors

• Sander Rainald
• Chen Liu
• Lee Teck Sim

Classifications

• H10W90/767

  between a chip and a laterally-adjacent lead frame, conducting package substrate or heat sink · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title