Resistive memory cell having a compact structure

Patent metadata

Field	Value
Publication number	US-10283563-B2
Application number	US-201715694463-A
Country	US
Kind code	B2
Filing date	Sep 1, 2017
Priority date	Jun 23, 2015
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

First claim

The invention claimed is:

1. A memory cell comprising:
a selection transistor having a control gate and a first conduction terminal;
a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includes:
a semiconductor substrate,
a first insulating layer covering the semiconductor substrate, and
a semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank,

a second insulating layer covering the lateral flank of the control gate,
a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wherein the variable-resistance element includes a layer of variable-resistance material positioned in the first trench along the lateral flank of the active layer, and
a trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material along the lateral flank of the active layer, wherein the lateral flank of the layer of variable-resistance material includes a lower flank and an upper flank, the lower flank contacting the trench conductor, the memory cell comprising a trench isolation positioned between the trench conductor and the upper flank.

2. The memory cell according to claim 1 , in which the layer of variable-resistance material is positioned between, and contacts, the trench isolation and the second insulating layer.

3. The memory cell according to claim 1 , in which the layer of variable-resistance material and the trench conductor contact the first insulating layer.

4. The memory cell according to claim 1 , in which the substrate, the active layer and the first insulating layer together form an FDSOI substrate.

5. The memory cell according to claim 1 , in which the second insulating layer and the layer of variable-resistance material covers a portion of a top of the control gate.

6. The memory cell according to claim 1 , further comprising:
a source line coupled a second conduction terminal of the selection transistor;
a bit line coupled to the trench conductor; and
a word line coupled to the control gate.

7. The memory cell according to claim 1 , in which the selection transistor includes a second conduction terminal, the second conduction terminal shared with an adjacent memory cell.

8. A memory, comprising:
a semiconductor substrate;
a first insulating layer covering the semiconductor substrate;
a semiconductor active layer covering the first insulating layer; and
a first memory cell that includes:
a selection transistor having a control gate positioned on the semiconductor active layer and a first conduction terminal positioned in the semiconductor active layer, the control gate having a lateral flank;
a variable-resistance element extending through the semiconductor active layer and contacting the first conduction terminal; and

a second insulating layer positioned between the lateral flank of the control gate, and the variable-resistance element, wherein the variable-resistance element includes:
a layer of variable-resistance material contacting a lateral flank of the semiconductor active layer and the first insulating layer, and
a trench conductor formed against a lateral flank of the layer of variable-resistance material and contact the first insulating layer.

9. The memory of claim 8 , wherein the lateral flank of the layer of variable-resistance material includes a lower flank and an upper flank, the lower flank contacting the trench conductor, the first memory cell comprising a trench isolation positioned between the trench conductor and the upper flank.

10. The memory of claim 9 , in which the layer of variable-resistance material is positioned between, and contacts, the trench isolation and the second insulating layer.

11. The memory of claim 8 , further comprising
a second memory cell that includes:
a second selection transistor having a control gate and first and second conduction terminals, the first and second conduction terminals of the second selection transistor being positioned in the semiconductor layer;
a third insulating layer on a lateral sidewall of the control gate of the second selection transistor; and
a second variable-resistance element on the third insulating layer and extending through the semiconductor layer, the third insulating layer between the control gate of the second selection transistor and the second variable-resistance element, the trench conductor being in a trench in the semiconductor layer between the first variable-resistance element and the second variable-resistance element.

12. The memory of claim 11 , further comprising:
a source line being coupled to the second conduction terminals of the first and second memory cells;
a bit line being coupled to the trench conductor; and
first and second word lines being coupled to the control gates of the first and second memory cells, respectively.

13. A memory cell comprising:
a selection transistor having a control gate and a first conduction terminal;
a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includes:
a semiconductor substrate,
a first insulating layer covering the semiconductor substrate, and
a semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank,

a second insulating layer covering the lateral flank of the control gate,
a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wherein the variable-resistance element includes a layer of variable-resistance material positioned in the first trench along the lateral flank of the active layer, and
a trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material along the lateral flank of the active layer, wherein the layer of variable-resistance material and the trench conductor contact the first insulating layer.

14. The memory cell according to claim 13 , in which the substrate, the active layer and the first insulating layer together form an FDSOI substrate.

15. The memory cell according to claim 13 , in which the second insulating layer and the layer of variable-resistance material covers a portion of a top of the control gate.

16. The memory cell according to claim 13 , further comprising:
a source line coupled a second conduction terminal of the selection transistor;
a bit line coupled to the trench conductor; and
a word line coupled to the control gate.

17. A memory cell comprising:
a selection transistor having a control gate and a first conduction terminal;
a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includes:
a semiconductor substrate,
a first insulating layer covering the semiconductor substrate, and
a semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank,

a second insulating layer covering the lateral flank of the control gate,
a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wh

Assignees

• St Microelectronics Crolles 2 Sas
• St Microelectronics Rousset

Inventors

• Boivin Philippe
• Jeannot Simon

Classifications

• G11C2213/82

  Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials · CPC title

• H01L45/1226

  Electricity · mapped topic

• H01L45/1666

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title