Method for forming semiconductor device structure having conductive structure with twin boundaries

Patent metadata

Field	Value
Publication number	US-10283450-B2
Application number	US-201715672780-A
Country	US
Kind code	B2
Filing date	Aug 9, 2017
Priority date	Aug 21, 2015
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries. The forming the conductive structure includes: manipulating process conditions so as to promote formation of the twin boundaries and yet control a density of the twin boundaries to be outside a range for which a portion of a curve is an asymptote of a constant value, the curve representing values of an atomic migration ratio corresponding to values of the density of the twin boundaries.

First claim

What is claimed is:

1. A method for forming a semiconductor device structure, the method comprising:
forming a conductive structure over a substrate:
wherein the conductive structure includes twin boundaries; and
wherein the forming the conductive structure includes:
manipulating process conditions so as to promote formation of the twin boundaries and yet control a density of the twin boundaries to be outside a range for which a portion of a curve is an asymptote of a constant value, the curve representing values of a corresponding atomic migration ratio corresponding to values of the density of the twin boundaries.

2. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the forming a conductive structure over the substrate includes:
performing a pulse current type of electrodeposition process.

3. The method for forming a semiconductor device structure as claimed in claim 1 , wherein forming the conductive structure over the substrate includes:
forming a diffusion barrier layer; and
forming a conductive material over the diffusion barrier layer, wherein a lattice mismatch ratio between a lattice constant of the diffusion bather layer and a lattice constant of the conductive material is in a range from about 0.1% to about 6%.

4. The method for forming a semiconductor device structure as claimed in claim 3 , further comprising:
forming a glue layer between the diffusion barrier layer and the conductive material, wherein a lattice mismatch ratio between a lattice constant of the glue layer and the lattice constant of the conductive material is in a range from about 0.1% to about 6%.

5. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising:
forming a via-trench structure over the conductive structure, wherein the via-trench structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 μm −1 to about 250 μm −1 .

6. The method for forming a semiconductor device structure as claimed in claim 1 , wherein:
the manipulating process conditions achieves a density of the twin boundaries which is in a range from about 25 μm −1 to about 250 μm −1 .

7. A method for forming a semiconductor device structure, the method comprising:
forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries;
wherein the forming the conductive structure includes:
promoting formation of twin boundaries by manipulating conditions of an electrodeposition process at a controlled temperature and at a controlled current density and for a controlled time period; and

wherein the electrodeposition process is a pulse current type of electrodeposition thereof; and
wherein the manipulating conditions of an electrodeposition process includes at least one of:
controlling a temperature of an electrolyte to be less than or equal to about 5 degrees;
controlling a current density to be less than or equal to about 1.8 A/cm 2 ; or
controlling a period of time for operating the pulse current type of electrodeposition to be less than or equal to about 0.2 seconds.

8. The method for forming a semiconductor device structure as claimed in claim 7 , wherein at least one of the following conditions is true:
a range of the temperature is from about −5 degrees to about 5 degrees;
a range of the current density is from about 0.4 A/cm 2 to about 1.8 A/cm 2 ; or
a range of the period of time for operating the pulse current type of electrodeposition is about 0.02 seconds to about 0.2 seconds.

9. The method for forming a semiconductor device structure as claimed in claim 7 , wherein:
the forming the conductive structure includes:
forming a conductive layer over a substrate; and
performing an annealing process on the conductive layer;

the promoting formation of twin boundaries further includes:
manipulating conditions of the annealing process; and

the manipulating conditions of the annealing process includes:
controlling a temperature to be less than or equal to about 400 degrees; or
controlling a period of time for performing annealing is less than or equal to about 1 hour.

10. The method for forming a semiconductor device structure as claimed in claim 9 , wherein:
a range of the temperature is from about 150 degrees to about 400 degrees; or
a range of the period of time for performing annealing is about 1 minute to about 1 hour.

11. The method for forming a semiconductor device structure as claimed in claim 7 , wherein the forming the conductive structure over the substrate includes:
forming a diffusion barrier layer; and
forming a conductive material over the diffusion barrier layer, wherein a lattice mismatch ratio between a lattice constant of the diffusion barrier layer and a lattice constant of the conductive material is in a range from about 0.1% to about 6%.

12. The method for forming a semiconductor device structure as claimed in claim 11 , further comprising:
forming a glue layer between the diffusion barrier layer and the conductive material, wherein a lattice mismatch ratio between a lattice constant of the glue layer and the lattice constant of the conductive material is in a range from about 0.1% to about 6%.

13. The method for forming a semiconductor device structure as claimed in claim 7 , further comprising:
forming a via-trench structure over the conductive structure, wherein the via-trench structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 μm −1 to about 250 μm −1 .

14. The method for forming a semiconductor device structure as claimed in claim 7 , wherein:
the forming the conductive structure achieves a density of the twin boundaries which is in a range from about 25 μm −1 to about 250 μm −1 .

15. The method for forming a semiconductor device structure as claimed in claim 2 , wherein:
a spacing between a first twin boundary and a second twin boundary is a twin-lamella width; and
the forming a conductive structure further includes:
manipulating process conditions so as to promote formation of twin-lamella widths within a range.

16. The method for forming a semiconductor device structure as claimed in claim 7 , wherein:
the manipulating conditions of an electrodeposition process includes at least two of:
controlling a temperature of an electrolyte to be less than or equal to about 5 degrees;
controlling a current density to be less than or equal to about 1.8 A/cm 2 ; or
controlling a period of time for operating the pulse current type of electrodeposition to be less than or equal to about 0.2 seconds.

17. A method for forming a semiconductor device structure, comprising:
forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries;
wherein a spacing between a first twin boundary and a second twin boundary is a twin-lamella width; and
wherein the forming the conductive structure includes:
manipulating process conditions so as to promote formation of twin-lamella widths within a range.

18. The method for forming a semiconductor device structure as claimed in claim 17 , wherein:
the forming a conductive structure includes:
performing an electrodeposition process; and

the manipulating process conditions includes:
controlling a range of a temperature to be from about −5 degrees to about 5 degrees;
controlling a range of a current density to be from about 0.4 A/cm 2 to about 1.8 A/cm 2 ; or
controlling a range of a period of time for operating the elect

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jian-Hong
• Chiu Chwei-Ching
• Lee Yung-Huei
• Liao Chien-Neng
• Chueh Yu-Lun
• Chan Tsung-Cheng
• Huang Chun-Lung

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title