Chip package having integrated capacitor

Patent metadata

Field	Value
Publication number	US-10283443-B2
Application number	US-201715474700-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Nov 10, 2009
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A semiconductor device includes a plurality of redistribution layers, a dielectric layer, and a conductive structure. The redistribution layers are formed overlying a device die to provide an electrical connection between the device die and an external connector in a package. The dielectric layer is arranged between the redistribution layers to form a capacitor structure. The conductive structure is formed and coupled between the device die and the redistribution layers.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of redistribution layers formed overlying a device die to provide an electrical connection between the device die and an external connector in a package, the plurality of redistribution layers comprising a first redistribution layer, a second redistribution layer and a third redistribution layer, wherein the third redistribution layer is formed overlying the second redistribution layer and coupled between the second redistribution layer and the external connector;
a dielectric layer arranged between and contacting the first redistribution layer and the second redistribution layer to form a capacitor structure;
a conductive structure formed and coupled between the device die and the plurality of redistribution layers, wherein the first redistribution layer is formed overlying the conductive structure; and
a first polymer layer formed between the second redistribution layer and the third redistribution layer.

2. The semiconductor device of claim 1 , further comprising:
a second polymer layer formed between the first redistribution layer and the conductive structure; and
a third polymer layer formed between the first redistribution layer and the second redistribution layer.

3. The semiconductor device of claim 1 , wherein a dielectric material of the dielectric layer comprises polyimide, polybenzoxazole, or a combination thereof.

4. The semiconductor device of claim 1 , wherein a dielectric material of the dielectric layer comprises SiNX, SiO2, SiOxNy, SrTiO3, or a combination thereof.

5. The semiconductor device of claim 1 , wherein a dielectric material of the dielectric layer comprises ZrO2, Al2O3, HfOx, HfSiOx, ZrTiOx, TiO2, TaOx, or a combination thereof.

6. The semiconductor device of claim 1 , wherein a dielectric material of the dielectric layer comprises ZrO2-Al2O3-ZrO2.

7. The semiconductor device of claim 1 , wherein a dielectric material of the dielectric layer comprises BaSrTiO3 (BST), PbZrTiO3 (PZT), PbZrLaTiO3, or a combination thereof.

8. The semiconductor device of claim 1 , wherein a dielectric material of the dielectric layer has a dielectric constant greater than 2.8.

9. A semiconductor device comprising:
a device die;
a first redistribution layer connected to the device die;
a first polymer layer over the first redistribution layer and having an opening to expose a portion of the first redistribution layer;
a dielectric layer over the exposed portion of the first redistribution layer and including a material different than the first polymer layer, the dielectric layer having a flat portion and an oblique portion adjacent to the flat portion and the flat portion of the dielectric layer is in contact with the first redistribution layer;
a second redistribution layer over the dielectric layer, the oblique portion of the dielectric layer being between the second redistribution layer and the first polymer layer; and
a second polymer layer over the second redistribution layer.

10. The semiconductor device of claim 9 , wherein a portion of the first polymer layer is between the dielectric layer and the first redistribution layer.

11. The semiconductor device of claim 9 , wherein the dielectric layer has a smaller length than the second redistribution layer.

12. A semiconductor device comprising:
a device die;
a first redistribution layer connected to the device die, wherein the first redistribution layer has a first portion, a second portion above the first portion, and a third portion between the first and second portions;
a first polymer layer over the first redistribution layer and having an opening to expose a portion of the first redistribution layer;
a second redistribution layer over the first redistribution layer;
a dielectric layer between the first and second redistribution layers and having a smaller thickness than at least one of the first and second redistribution layers, wherein the dielectric layer is in contact with the second portion of the first redistribution layer; and
a second polymer layer over the second redistribution layer.

13. The semiconductor device of claim 12 , wherein the dielectric layer has a smaller length than the second redistribution layer.

14. The semiconductor device of claim 12 , further comprising:
a molding compound surrounding the device die,
wherein the dielectric layer has a dielectric constant greater than that of the molding compound.

15. The semiconductor device of claim 12 , further comprising:
a third redistribution layer formed overlying the second redistribution layer and coupled between the second redistribution layer and an external connector in a package,
wherein the first polymer layer is formed between the second redistribution layer and the third redistribution layer.

16. The semiconductor device of claim 9 , further comprising:
a third redistribution layer formed overlying the second redistribution layer and coupled between the second redistribution layer and an external connector in a package,
wherein the first polymer layer is formed between the second redistribution layer and the third redistribution layer.

17. The semiconductor device of claim 2 , wherein the dielectric layer has a flat portion and an oblique portion adjacent to the flat portion, and the oblique portion of the dielectric layer is between the second redistribution layer and the third polymer layer.

18. The semiconductor device of claim 15 , wherein a flat portion of the dielectric layer is in contact with the first redistribution layer.

19. The semiconductor device of claim 1 , wherein the dielectric layer has a smaller thickness than at least one of the first and second redistribution layers.

20. The semiconductor device of claim 1 , wherein the dielectric layer has a smaller length than the second redistribution layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liao Wen-Shiang
• Jou Chewn-Pu

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title