Fan-Out Package and Methods of Forming Thereof

Patent metadata

Field	Value
Publication number	US-2016005702-A1
Application number	US-201414322842-A
Country	US
Kind code	A1
Filing date	Jul 2, 2014
Priority date	Jan 17, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening.

First claim

What is claimed is:

1 . A package comprising:
a chip comprising a substrate and a contact pad on the substrate; a molding compound laterally encapsulating the chip; a first dielectric layer overlying the molding compound and the chip and having a first opening exposing the contact pad; a first metallization layer overlying the first dielectric layer, wherein the first metallization layer fills the first opening and laterally extends over the molding compound; a second dielectric layer overlying the first metallization layer and the first dielectric layer and having a second opening over the first opening; and a second metallization layer overlying the second dielectric layer and electrically coupled to the first metallization layer through the second opening and laterally extends over the molding compound.

2 . The package of claim 1 , wherein the second metallization layer is formed in the second opening and physically contacts the first metallization layer.

3 . The package of claim 1 , wherein the second metallization layer lines a sidewall and a bottom of the second opening.

4 . The package of claim 1 , wherein the first metallization layer comprises a first seed layer and a first conductive layer formed on the first seed layer.

5 . The package of claim 4 , wherein the first seed layer comprises titanium and the first conductive layer comprises copper.

6 . The package of claim 1 , wherein the second metallization layer comprises a second seed layer and a second conductive layer formed on the second seed layer.

7 . The package of claim 6 , wherein the second seed layer comprises titanium and the second conductive layer comprises copper.

8 . The package of claim 1 , further comprising a bump on the second metallization layer.

9 . The package of claim 9 , further comprising a protection layer overlying the second metallization layer and the second dielectric layer and around a portion of the bump.

10 . The package of claim 1 , wherein the chip comprises a passivation layer on the substrate and covering a portion of the contact pad, and the first dielectric layer is formed overlying the passivation layer.

11 . A package comprising:
a chip comprising a substrate and a contact pad on the substrate; a molding compound laterally encapsulating the chip; a first dielectric layer overlying the molding compound and the chip and having a first opening exposing the contact pad; a first seed layer overlying the first dielectric layer and lining a sidewall and a bottom of the first opening; a first conductive layer overlying the first seed layer and filling the first opening; a second dielectric layer overlying the first conductive layer and having a second opening directly over the first opening; and a second seed layer overlying the second dielectric layer and lining a sidewall and a bottom of the second opening; and a second conductive layer overlying the second seed layer.

12 . The package of claim 11 , wherein the second conductive layer is formed along the sidewall and the bottom of the second opening.

13 . The package of claim 11 , wherein the first seed layer comprises titanium and the first conductive layer comprises copper.

14 . The package of claim 11 , wherein the second seed layer comprises titanium and the second conductive layer comprises copper.

15 . The package of claim 11 , further comprising a bump on the second conductive layer.

16 . The package of claim 15 , further comprising a protection layer overlying the second conductive layer and the second dielectric layer and around a portion of the bump.

17 . A method comprising:
providing a chip with a contact pad; forming a molding compound laterally encapsulating the chip, the contact pad being exposed through the molding compound; forming a first dielectric layer over the molding compound and the chip; forming a first opening in the first dielectric layer, exposing the contact pad; forming a first conductive layer overlying the first dielectric layer and filling the first opening, wherein the first conductive layer in the first opening has a flat surface; forming a second dielectric layer over the first conductive layer and the first dielectric layer; forming a second opening in the second dielectric layer exposing the first conductive layer over the first opening; and forming a second conductive layer overlying the second dielectric layer and physically contacting the first conductive layer through the second opening.

18 . The method of claim 17 , wherein the first conductive layer is formed by a copper plating process with a plating rate greater than 1 μm/min.

19 . The method of claim 17 , wherein the first conductive layer formed in the first opening has a width (W) and a height (H), and the ratio of W/H is less than 20.

20 . The method of claim 17 , wherein the first conductive layer formed in the first opening has a width (W) and a height (H), and the ratio of W/H is greater than 2.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Shih Wan-Ting
• Liu Nai-Wei
• Lin Jing-Cheng
• Huang Cheng-Lin

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/655

  Fan-out layouts · CPC title