Semiconductor device and method of forming stress relief layer between die and interconnect structure

Patent metadata

Field	Value
Publication number	US-9006888-B2
Application number	US-201113248312-A
Country	US
Kind code	B2
Filing date	Sep 29, 2011
Priority date	Jun 11, 2008
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

First claim

What is claimed:

1. A semiconductor device, comprising:
a semiconductor die;
a plurality of conductive pillars formed around the semiconductor die;
a conductive layer formed over the conductive pillars and vertically offset from the semiconductor die;
a stress relief insulating layer formed over the semiconductor die and the conductive layer, the stress relief insulating layer including a first thickness over the semiconductor die and a second thickness less than the first thickness over the conductive layer;
an encapsulant deposited over the semiconductor die and around the conductive pillars;
a first interconnect structure formed over the stress relief insulating layer; and
a second interconnect structure formed over the encapsulant opposite the stress relief insulating layer.

2. The semiconductor device of claim 1 , wherein the second interconnect structure includes an integrated passive device.

3. The semiconductor device of claim 1 , wherein a back surface of the semiconductor die opposite an active surface of the semiconductor die is coplanar with a surface of the conductive pillars opposite the stress relief insulating layer.

4. The semiconductor device of claim 1 , further including a plurality of the semiconductor devices stacked and electrically connected through the conductive pillars.

5. The semiconductor device of claim 1 , wherein the first interconnect structure is electrically connected to the second interconnect structure through the conductive pillars.

6. The semiconductor device of claim 1 , further including a plurality of conductive bumps formed over the first interconnect structure.

7. The semiconductor device of claim 1 , wherein:
the first thickness of the stress relief insulating layer includes a range of 5-100 μm; and
the second thickness of the stress relief insulating layer includes a range of 2-50 μm.

8. A semiconductor device, comprising:
a semiconductor die;
a conductive pillar formed around the semiconductor die;
a stress relief insulating layer formed over the semiconductor die and the conductive pillar, the stress relief insulating layer including a first thickness over the semiconductor die and a second thickness less than the first thickness over the conductive pillar;
an encapsulant deposited over the semiconductor die and around the conductive pillar; and
a first interconnect structure formed over the stress relief insulating layer.

9. The semiconductor device of claim 8 , further including a second interconnect structure including an integrated passive device formed over the encapsulant opposite the stress relief insulating layer.

10. The semiconductor device of claim 8 , wherein a back surface of the semiconductor die opposite an active surface of the semiconductor die is coplanar with a surface of the conductive pillar opposite the stress relief insulating layer.

11. The semiconductor device of claim 8 , further including a plurality of the semiconductor devices stacked and electrically connected through the conductive pillar.

12. The semiconductor device of claim 9 , wherein the first interconnect structure is electrically connected to the second interconnect structure through the conductive pillar.

13. The semiconductor device of claim 8 , further including a conductive bump formed over the first interconnect structure.

14. The semiconductor device of claim 8 , wherein:
the first thickness of the stress relief insulating layer includes a range of 5-100 μm; and
the second thickness of the stress relief insulating layer includes a range of 2-50 μm.

15. A semiconductor device, comprising:
a semiconductor die;
a conductive pillar formed around the semiconductor die;
a stress relief insulating layer formed over the semiconductor die and the conductive pillar including an opening in the stress relief insulating layer over the semiconductor die; and
a first interconnect structure formed over the stress relief insulating layer.

16. The semiconductor device of claim 15 , further including:
an encapsulant deposited over the semiconductor die and around the conductive pillar;
a second interconnect structure formed over the encapsulant opposite the stress relief insulating layer; and
an integrated passive device formed over the second interconnect structure.

17. The semiconductor device of claim 15 , wherein a back surface of the semiconductor die opposite an active surface of the semiconductor die is coplanar with a surface of the conductive pillar opposite the stress relief insulating layer.

18. The semiconductor device of claim 15 , further including a plurality of the semiconductor devices stacked and electrically connected through the conductive pillar.

19. The semiconductor device of claim 15 , further including a second interconnect structure formed over the semiconductor die opposite the stress relief insulating layer and electrically connected to the first interconnect structure through the conductive pillar.

20. The semiconductor device of claim 15 , wherein the stress relief insulating layer includes a first thickness over the semiconductor die and a second thickness less than the first thickness over the conductive pillar.

21. A semiconductor device, comprising:
a semiconductor die;
a conductive pillar formed around the semiconductor die; and
a stress relief insulating layer formed over the semiconductor die and the conductive pillar including an opening in the stress relief insulating layer over the semiconductor die.

22. The semiconductor device of claim 21 , further including:
an encapsulant deposited over the semiconductor die and around the conductive pillar;
a first interconnect structure formed over the stress relief insulating layer;
a second interconnect structure formed over the encapsulant opposite the stress relief insulating layer; and
an integrated passive device formed over the second interconnect structure.

23. The semiconductor device of claim 21 , wherein a back surface of the semiconductor die opposite an active surface of the semiconductor die is coplanar with a surface of the conductive pillar opposite the stress relief insulating layer.

24. The semiconductor device of claim 21 , further including a plurality of the semiconductor devices stacked and electrically connected through the conductive pillar.

25. The semiconductor device of claim 21 , wherein the stress relief insulating layer includes a first thickness over the semiconductor die and a second thickness less than the first thickness over the conductive pillar.

Assignees

• Shim Il Kwon
• Chow Seng Guan
• Lin Yaojian
• Stats Chippac Ltd

Inventors

• Shim Il Kwon
• Chow Seng Guan
• Lin Yaojian

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9413

  on encapsulations · CPC title