Fan-out semiconductor package including electromagnetic interference shielding layer

Patent metadata

Field	Value
Publication number	US-10283439-B2
Application number	US-201816001430-A
Country	US
Kind code	B2
Filing date	Jun 6, 2018
Priority date	Dec 22, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a core member having a first through-hole;
a semiconductor chip disposed in the first through-hole of the core member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the core member and the inactive surface of the semiconductor chip;
a connection member disposed on the core member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip;
a metal layer disposed on walls of the first through-hole of the core member and extending to at least one surface of the first connection member;
an electromagnetic interference (EMI) shielding layer disposed on the encapsulant and covering at least the inactive surface of the semiconductor chip; and
vias penetrating through the encapsulant and connecting the EMI shielding layer to the metal layer.

2. The fan-out semiconductor package of claim 1 , wherein the metal layer and the EMI shielding layer are electrically connected to ground patterns formed in the fan-out semiconductor package.

3. The fan-out semiconductor package of claim 1 , wherein the connection member further includes a heat dissipation vias connected to the active surface of the semiconductor chip.

4. The fan-out semiconductor package of claim 1 , wherein the core member further has a second through-hole, and
a second passive component is disposed in the second through-hole.

5. The fan-out semiconductor package of claim 4 , wherein a first passive component is disposed in the core member, and
the second passive component has a thickness greater than that of the first passive component.

6. The fan-out semiconductor package of claim 5 , wherein a lower surface of the first passive component is disposed on a level above a lower surface of the second passive component, with respect to the connection member.

7. The fan-out semiconductor package of claim 1 , further comprising an electronic component disposed in the first through-hole.

8. The fan-out semiconductor package of claim 7 , wherein the electronic component is at least one of an integrated circuit, a passive component, or a dummy chip.

9. The fan-out semiconductor package of claim 1 , wherein the core member includes an insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, and
the first and second redistribution layers of the core member are electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the connection member.

10. The fan-out semiconductor package of claim 1 , wherein the encapsulant includes a first encapsulant disposed on the core member and having a through-hole overlapping the first through-hole of the core member in a direction along which the semiconductor chip and the connection member are stacked, and a second encapsulant disposed on the first encapsulant and encapsulating at least portions of the semiconductor chip.

Assignees

• Samsung Electro Mech

Inventors

• Cho Jung Hyun
• Baek Yong Ho
• Hwang Jun Oh
• Jung Joo Hwan
• Yi Moon Hee

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title