Middle of the line (MOL) contacts with two-dimensional self-alignment

Patent metadata

Field	Value
Publication number	US-10283408-B2
Application number	US-201715851774-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Dec 22, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.

First claim

What is claimed is:

1. An integrated circuit structure comprising:
a semiconductor body comprising a channel region positioned laterally between source/drain regions;
a gate above the channel region;
a gate sidewall spacer positioned laterally adjacent to sidewalls of the gate;
a dielectric cap above and immediately adjacent to a top surface of the gate;
a dielectric spacer above and immediately adjacent to a top surface of the gate sidewall spacer and laterally surrounding and immediately adjacent to sidewalls of the dielectric cap;
metal plugs above the source/drain regions and positioned laterally adjacent to the dielectric spacer;
at least one dielectric layer above the dielectric cap, the dielectric spacer and the metal plugs;
wires in an upper portion of the at least one dielectric layer; and
contacts that extend from the wires through a lower portion of the at least one dielectric layer,
wherein the contacts comprise at least a first contact and a second contact,
wherein the first contact extends through the lower portion of the at least one dielectric layer and through the dielectric cap to the gate,
wherein the second contact extends through the lower portion to one of the metal plugs, and
wherein the dielectric cap, the dielectric spacer, and the at least one dielectric layer all comprise different dielectric materials.

2. The integrated circuit structure of claim 1 , wherein the different dielectric materials ensure that the first contact and the second contact are self-aligned.

3. The integrated circuit structure of claim 1 , wherein the first contact lands on the gate adjacent to an active region.

4. The integrated circuit structure of claim 1 ,
wherein the at least one dielectric layer comprises an interlayer dielectric layer, and
wherein the different dielectric materials comprise silicon oxide for the interlayer dielectric layer, silicon nitride for the dielectric cap and silicon oxycarbide for the dielectric spacer.

5. The integrated circuit structure of claim 1 , wherein the dielectric cap and the gate sidewall spacer comprise a same dielectric material.

6. The integrated circuit structure of claim 1 , wherein the dielectric cap comprises a different dielectric material than the gate sidewall spacer.

7. An integrated circuit structure comprising:
a semiconductor body comprising a channel region positioned laterally between source/drain regions;
a gate above the channel region;
a gate sidewall spacer on sidewalls of the gate, wherein top surfaces of the gate sidewall spacer and the gate are approximately level;
a dielectric cap above and immediately adjacent to a top surface of the gate;
a dielectric spacer above and immediately adjacent to a top surface of the gate sidewall spacer and further laterally surrounding and immediately adjacent to sidewalls of the dielectric cap, wherein the dielectric cap and the dielectric spacer have essentially equal heights as measured from the top surface of the gate and the top surface of the gate sidewall spacer, respectively;
a first layer of interlayer dielectric material positioned laterally adjacent to the gate sidewall spacer and the dielectric cap above the gate sidewall spacer, wherein top surfaces of the dielectric cap and the first layer of interlayer dielectric material are essentially co-planar;
metal plugs in openings that extend through the first layer of interlayer dielectric material to the source/drain regions such that the metal plugs are positioned laterally adjacent to the gate sidewall spacer and the dielectric spacer;
a second layer of interlayer dielectric material above the first layer of interlayer dielectric material, the dielectric cap, the dielectric spacer and the metal plugs;
wires in an upper portion of the second layer of interlayer dielectric material; and
contacts that extend from the wires through a lower portion of the second layer of interlayer dielectric material,
wherein the contacts comprise at least a first contact and a second contact,
wherein the first contact extends through the lower portion of the second layer of interlayer dielectric material and through the dielectric cap to the gate,
wherein the second contact extends through the lower portion of the second layer of interlayer dielectric material to one of the metal plugs, and
wherein the dielectric cap, the dielectric spacer, and the first interlayer dielectric material comprise different dielectric materials.

8. The integrated circuit structure of claim 7 , wherein the different dielectric materials ensure that the first contact and the second contact are self-aligned.

9. The integrated circuit structure of claim 7 , wherein the first contact lands on the gate adjacent to an active region.

10. The integrated circuit structure of claim 7 ,
wherein the different dielectric materials comprise silicon oxide for the interlayer dielectric material, silicon nitride for the dielectric cap and silicon oxycarbide for the dielectric spacer.

11. The integrated circuit structure of claim 7 , wherein the dielectric cap and the gate sidewall spacer comprise a same dielectric material.

12. The integrated circuit structure of claim 7 , wherein the dielectric cap comprises a different dielectric material than the gate sidewall spacer.

13. The integrated circuit structure of claim 7 ,
wherein the gate sidewall spacer comprises any of silicon nitride, silicon carbon nitride and silicon boron carbon nitride,
wherein the dielectric cap comprises silicon nitride,
wherein the dielectric spacer comprises silicon oxycarbide, and
wherein the interlayer dielectric material comprises silicon dioxide.

14. An integrated circuit structure comprising:
multiple parallel fin-shaped semiconductor bodies, each semiconductor body comprising multiple channel regions and each channel region being positioned laterally between source/drain regions, wherein the multiple channel regions comprise pairs of adjacent channel regions and the source/drain regions comprise shared source/drain region positioned laterally between each of the pairs of adjacent channel regions;
gates traversing the semiconductor bodies such that each gate is adjacent to adjacent channel regions on adjacent semiconductor bodies;
gate sidewall spacers positioned laterally adjacent to sidewalls of the gates;
dielectric caps above and immediately adjacent to top surfaces of the gates;
dielectric spacers above and immediately adjacent to the gate sidewall spacers and laterally surrounding and immediately adjacent to sidewalls of the dielectric caps;
metal plugs above the source/drain regions;
at least one dielectric layer above the dielectric caps, the dielectric spacers and the metal plugs;
wires in an upper portion of the at least one dielectric layer; and
contacts that extend from the wires through a lower portion of the at least one dielectric layer,
wherein the contacts comprise at least a first contact and a second contact,
wherein the first contact extends through the lower portion of the at least one dielectric layer and through one of the dielectric caps to one of the gates,
wherein the second contact extends through the lower portion of the at least one dielectric layer to one of the metal plugs, and
wherein the dielectric caps, the dielectric spacers, and the at least one dielectric layer comprise different dielectric materials.

15. The integrated circuit structure of claim 14 , wherein the different dielectric materials ensure that the first contact and the second contact are self-aligned.

16. The integrated circuit structure of claim 14 , w

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Park Chanro
• Labonte Andre
• Liebmann Lars

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/085

  involving intermediate temporary filling with material · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/48

  Insulating materials thereof · CPC title