Nonvolatile memory device and related method of operation

Patent metadata

Field	Value
Publication number	US-9053794-B2
Application number	US-201213540951-A
Country	US
Kind code	B2
Filing date	Jul 3, 2012
Priority date	Oct 19, 2011
Publication date	Jun 9, 2015
Grant date	Jun 9, 2015

Abstract

A nonvolatile memory comprises a memory block having memory cells stacked in a three dimensional structure. The nonvolatile memory device performs an erase operation to erase a selected sub block among sub blocks of the memory block, a verification operation to determine whether program states of memory cells of an unselected sub block of the memory block have changed as a consequence of the erase operation, and a reprogramming operation to reprogram at least a portion of the unselected sub block upon determining that at least one of the program states have changed as a consequence of the erase operation.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory device comprising a memory block having memory cells stacked in a three dimensional structure, the method comprising:
performing an erase operation to erase a selected sub block among sub blocks of the memory block;
performing a verification operation comprising determining whether program states of memory cells of an unselected sub block of the memory block have changed as a consequence of the erase operation; and
performing a reprogramming operation to reprogram at least a portion of the unselected sub block upon determining that at least one of the program states have changed as a consequence of the erase operation.

2. The method of claim 1 , wherein each of the sub blocks comprises multiple cell strings arranged in a direction perpendicular to a substrate.

3. The method of claim 1 , wherein the verification operation comprises determining target program states of the memory cells of the unselected sub block.

4. The method of claim 1 , wherein the verification operation is performed using a selection read voltage and a program verification voltage corresponding to program states of the memory cells and wherein program states are determined to be changed where threshold voltages of the memory cells are higher than the selection read voltage and lower than the program verification voltage.

5. The method of claim 1 , wherein the reprogramming operation is performed without input data from a source external to the nonvolatile memory device.

6. The method of claim 1 , further comprising, before the erase operation, reading data stored in memory cells of the unselected sub block.

7. The method of claim 6 , further comprising temporarily storing the data read from the memory cells of the unselected sub block in a read circuit of the nonvolatile memory device until the reprogramming operation is completed.

8. The method of claim 7 , further comprising performing the reprogramming operation using the data temporarily stored in the read circuit.

9. The method of claim 6 , further comprising performing the verification operation using a program verification voltage corresponding to program states of the memory cells and determining that the program states are changed where threshold voltages of the memory cells are lower than the program verification voltage.

10. The method of claim 1 , further comprising an erase verification operation comprising verifying whether the selected sub block is successfully erased.

11. The method of claim 10 , wherein the erase operation and the erase verification operation are performed in successive loops until the selected sub block is successfully erased, and the reprogramming operation is performed thereafter.

12. A nonvolatile memory device, comprising:
a memory cell array comprising a memory block having memory cells stacked in a three dimensional structure; and
a controller configured to control the memory cell array such that sub blocks of the memory block are erased independent of each other, wherein an erase operation erases a selected sub block among sub blocks of the memory block, a verification operation determines whether program states of memory cells of an unselected sub block of the memory block have changed as a consequence of the erase operation, and a reprogramming operation that reprograms at least a portion of the unselected sub block upon determining that at least one of the program states have changed as a consequence of the erase operation.

13. The nonvolatile memory device of claim 12 , wherein the sub blocks are configured to share string select transistors and ground select transistors of the memory block.

14. The nonvolatile memory device of claim 12 , wherein the controller is configured to apply a program pulse without requiring data input from a source external to the nonvolatile memory device.

15. The nonvolatile memory device of claim 12 , wherein the controller is configured to reprogram at least a portion the unselected sub block comprising memory cells having program states determined to be changed according to the verification operation.

16. The nonvolatile memory device of claim 12 , further comprising a read/write circuit configured to write data in the memory cell array or read data from the memory cell array before erasing the selected sub block, wherein the controller is configured to temporarily store data from memory cells of the unselected sub block in the read/write circuit and to reprogram the unselected sub block using the temporarily stored data.

17. A method of operating a nonvolatile memory device comprising a memory block formed in a stacked three dimensional structure, comprising:
storing a backup copy of data stored in a first sub block of the memory block;
erasing a second sub block of the memory block located adjacent to the first sub block; and
reprogramming the first sub block based on the backup copy after erasing the second sub block.

18. The method of claim 17 , wherein the first and second sub blocks each comprise a plurality of NAND strings arranged perpendicular to a substrate.

19. The method of claim 17 , further comprising determining whether the second sub block has been successfully erased, and reprogramming the first sub block as a consequence of determining that the second sub block has been successfully erased.

20. The method of claim 17 , further comprising verifying whether program states of memory cells in the first sub block have changed as a consequence of erasing the second sub block, and reprogramming the first sub block as a consequence of determining that the program states of at least one memory cell in the first sub block has changed as a consequence of erasing the second sub block.

Assignees

• Kwak Dong-Hun
• Samsung Electronics Co Ltd

Inventors

• Kwak Dong-Hun

Classifications

• H01L27/11582

  Electricity · mapped topic

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• H01L27/1157

  Electricity · mapped topic

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title