Electronic component embedded substrate

Patent metadata

Field	Value
Publication number	US-10278290-B2
Application number	US-201715654281-A
Country	US
Kind code	B2
Filing date	Jul 19, 2017
Priority date	Jul 19, 2016
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

An electronic component embedded substrate 1 includes a substrate 10 having a wiring layer 11 and an insulating layer 12; an electronic component 20 built in the substrate 10, and having a pair of electrode layers 21A and 21B, and a dielectric layer 22; and a stress relieving layer 30 provided closer to the wiring layer 11 than the insulating layer 12 is in the lamination direction, wherein at least part of an end portion of the electronic component 20 on the wiring layer 11 side is in contact with the stress relieving layer 30, wherein at least part of an end portion of the electronic component 20 on the insulating layer 12 side is in contact with the insulating layer 12, and wherein the Young's modulus of the stress relieving layer 30 is lower than the Young's modulus of the electrode layer 21B.

First claim

What is claimed is:

1. An electronic component embedded substrate comprising:
a substrate having a wiring layer and an insulating layer laminated on the wiring layer;
an electronic component built in the substrate, and having a pair of electrode layers extending in a direction intersecting with a lamination direction of the substrate, and a dielectric layer provided between the pair of electrode layers; and
a stress relieving layer provided closer to the wiring layer than the insulating layer is in the lamination direction, wherein:
at least part of an end portion of the electronic component on the wiring layer side is in contact with the stress relieving layer in the lamination direction;
at least part of an end portion of the electronic component on the insulating layer side is in contact with the insulating layer in the lamination direction;
a Young's modulus of the stress relieving layer is lower than a Young's modulus of an electrode layer of the pair of electrode layers positioned on the wiring layer side;
the stress relieving layer includes a first stress relieving layer having insulating properties and a second stress relieving layer having conductivity; and
the second stress relieving layer is provided closer to an exposed surface of the wiring layer than the electrode layer positioned on the wiring layer side.

2. The electronic component embedded substrate according to claim 1 ,
wherein at least part of the electronic component is embedded in the wiring layer, and
the stress relieving layer is exposed from the wiring layer side of the electronic component embedded substrate.

3. The electronic component embedded substrate according to claim 1 ,
wherein the stress relieving layer and the electronic component are sequentially laminated on the wiring layer, and
the stress relieving layer is in contact with the wiring layer.

4. The electronic component embedded substrate according to claim 3 , wherein the Young's modulus of the stress relieving layer is lower than a Young's modulus of the wiring layer.

5. The electronic component embedded substrate according to claim 1 , wherein the stress relieving layer has insulation.

6. The electronic component embedded substrate according to claim 1 , wherein:
the stress relieving layer is closer to an exposed surface of the wiring layer than the electrode layer of the pair of electrode layers positioned on the wiring layer side; and
the stress relieving layer has conductivity.

7. An electronic component embedded substrate comprising:
a substrate having a wiring layer and an insulating layer laminated on the wiring layer;
an electronic component built in the substrate, and having a pair of electrode layers extending in a direction intersecting with a lamination direction of the substrate, and a dielectric layer provided between the pair of electrode layers; and
a stress relieving layer provided closer to the wiring layer than the insulating layer is in the lamination direction, wherein:
at least part of an end portion of the electronic component on the wiring layer side is in contact with the stress relieving layer in the lamination direction;
at least part of an end portion of the electronic component on the insulating layer side is in contact with the insulating layer in the lamination direction;
a Young's modulus of the stress relieving layer is lower than a Young's modulus of an electrode layer of the pair of electrode layers positioned on the wiring layer side;
at least part of the electronic component is embedded in the wiring layer; and
the stress relieving layer is exposed from the wiring layer side of the electronic component embedded substrate.

8. The electronic component embedded substrate according to claim 7 ,
wherein the stress relieving layer and the electronic component are sequentially laminated on the wiring layer, and
the stress relieving layer is in contact with the wiring layer.

9. The electronic component embedded substrate according to claim 8 , wherein the Young's modulus of the stress relieving layer is lower than a Young's modulus of the wiring layer.

10. The electronic component embedded substrate according to claim 7 , wherein the Young's modulus of the stress relieving layer is lower than a Young's modulus of the insulating layer.

11. The electronic component embedded substrate according to claim 7 , wherein the stress relieving layer has insulation.

12. The electronic component embedded substrate according to claim 7 , wherein:
the stress relieving layer is closer to an exposed surface of the wiring layer than the electrode layer of the pair of electrode layers positioned on the wiring layer side; and
the stress relieving layer has conductivity.

13. An electronic component embedded substrate comprising:
a substrate having a wiring layer and an insulating layer laminated on the wiring layer;
an electronic component built in the substrate, and having a pair of electrode layers extending in a direction intersecting with a lamination direction of the substrate, and a dielectric layer provided between the pair of electrode layers; and
a stress relieving layer provided closer to the wiring layer than the insulating layer is in the lamination direction, wherein:
at least part of an end portion of the electronic component on the wiring layer side is in contact with the stress relieving layer in the lamination direction;
at least part of an end portion of the electronic component on the insulating layer side is in contact with the insulating layer in the lamination direction;
a Young's modulus of the stress relieving layer is lower than a Young's modulus of an electrode layer of the pair of electrode layers positioned on the wiring layer side; and
the Young's modulus of the stress relieving layer is lower than a Young's modulus of the insulating layer.

14. The electronic component embedded substrate according to claim 13 ,
wherein at least part of the electronic component is embedded in the wiring layer, and
the stress relieving layer is exposed from the wiring layer side of the electronic component embedded substrate.

15. The electronic component embedded substrate according to claim 13 ,
wherein the stress relieving layer and the electronic component are sequentially laminated on the wiring layer, and
the stress relieving layer is in contact with the wiring layer.

16. The electronic component embedded substrate according to claim 15 , wherein the Young's modulus of the stress relieving layer is lower than a Young's modulus of the wiring layer.

17. The electronic component embedded substrate according to claim 13 , wherein the Young's modulus of the stress relieving layer is lower than a Young's modulus of the insulating layer.

18. The electronic component embedded substrate according to claim 13 , wherein the stress relieving layer has insulation.

19. The electronic component embedded substrate according to claim 13 , wherein:
the stress relieving layer is closer to an exposed surface of the wiring layer than the electrode layer of the pair of electrode layers positioned on the wiring layer side; and
the stress relieving layer has conductivity.

Assignees

• Tdk Corp

Inventors

• Yoshida Kenichi
• Tomikawa Mitsuhiro

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/01336

  in solid form, e.g. by using a powder or by laminating a foil · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W70/614 Primary

  the multiple chips being integrally enclosed · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title