Memory device having self-aligned cell structure

Patent metadata

Field	Value
Publication number	US-10276635-B2
Application number	US-201313959431-A
Country	US
Kind code	B2
Filing date	Aug 5, 2013
Priority date	Feb 6, 2009
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.

First claim

What is claimed is:

1. An apparatus comprising:
diodes arranged in rows and columns, each of the diodes including a first material of a first conductivity type and a second material of a second conductivity type;
first trenches filled with a first insulation material, each of the first trenches being located between two of the rows;
second trenches filled with a second insulation material, each of the second trenches being located between two of the columns, wherein the first and second materials of at least one of the diodes contact the first insulation material in at least one of the first trenches and the second insulation material in at least one of the second trenches; and
memory elements coupled to the diodes, wherein each of the memory elements contacts the first insulation material on a sidewall in at least one of the first trenches and contacts the second insulation material on a sidewall in at least one of the second trenches.

2. The apparatus of claim 1 , wherein the diodes include a group of diodes arranged in one of the rows, and wherein each diode in the group of diodes includes a first diode terminal coupled to a first conductive line and a second diode terminal coupled to a second conductive line.

3. The apparatus of claim 2 , wherein the first conductive line is perpendicular to the second conductive line.

4. The apparatus of claim 2 , wherein each of the memory elements is coupled between the first conductive line and one diode of the group of diodes.

5. The apparatus of claim 1 , wherein the memory elements include a chalcogenide material.

6. The apparatus of claim 1 , wherein a thickness of the first insulation material is greater than a thickness of the second insulation material.

7. The apparatus of claim 1 , wherein at least one of the second trenches includes a bottom coupled to a conductive material.

8. An apparatus comprising:
diodes arranged in rows and columns, each of the diodes including a first material of a first conductivity type and a second material of a second conductivity type;
first trenches filled with a first insulation material, each of the first trenches being located between two of the rows;
second trenches filled with a second insulation material, each of the second trenches being located between two of the columns, wherein the first and second materials of at least one of the diodes contact the first insulation material in at least one of the first trenches and the second insulation material in at least one of the second trenches; and
memory elements coupled to the diodes, wherein each of the memory elements contacts the first insulation material on a sidewall in at least one of the first trenches and contacts the second insulation material on a sidewall in at least one of the second trenches, wherein at least one of the second trenches includes a bottom coupled to a conductive material, and the conductive material includes a combination of cobalt and silicon.

9. An apparatus comprising:
recesses arranged in rows and columns;
diodes formed in the recesses;
first trenches filled with a first insulation material;
second trenches filled with a second insulation material, wherein each of the recessed is defined by a sidewall portion of at least one of the first trenches and a sidewall portion of at least one of the second trenches, wherein the diodes contact the first insulation material in at least one of the first trenches and the second insulation material in at least one of the second trenches;
memory elements formed in the recesses, the memory elements coupled to the diodes, wherein each of the memory elements contacts the first insulation material in at least one of the first trenches and contacts the second insulation material in at least one of the second trenches; and
a conductive material formed outside the recesses and between the diodes and a substrate, wherein the conductive material is directly coupled to at least one diode of the diodes.

10. The apparatus of claim 9 , further comprising:
first trenches filled with a first insulation material; and
second trenches filled with a second insulation material, wherein each of the recesses is defined by a sidewall portion of at least one of the first trenches and a sidewall portion of at least one of the second trenches.

11. The apparatus of claim 9 , wherein the first and second insulation material include a same material.

12. The apparatus of claim 9 , wherein the first and second insulation material include different materials.

13. The apparatus of claim 9 , further comprising a conductive material formed in the recesses, wherein the conductive material is between one of the memory elements in one of the recesses and one of the diodes in one of the recesses.

14. The apparatus of claim 9 , wherein the conductive material includes silicon.

15. A method comprising:
forming diodes in rows and columns such that each of the diodes includes a first material of a first conductivity type and a second material of a second conductivity type:
forming first trenches filled with a first insulation material, each of the first trenches being located between two of the rows;
forming second trenches filled with a second insulation material, each of the second trenches being located between two of the columns, wherein the first and second materials of at least one of the diodes contact the first insulation material in at least one of the first trenches and the second insulation material in at least one of the second trenches; and
forming memory elements coupled to the diodes, wherein each of the memory elements contacts the first material on a sidewall in at least one of the first trenches and the second insulation material on a sidewall in at least one of the second trenches.

16. The method of claim 15 , wherein the first material includes n-type silicon material and the second conductive material includes p-type silicon material.

17. The method of claim 16 , further comprising:
forming a conductive material coupled to the diodes, wherein the conductive material includes n-type silicon material.

18. The method of claim 17 , wherein the conductive material is formed between the diodes and a substrate.

19. The method of claim 18 , wherein the substrate includes p-type silicon material.

Assignees

• Micron Technology Inc

Inventors

• Liu Jun
• Violette Michael P

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L45/144

  Electricity · mapped topic

• H01L45/141

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic