Mounting component, wiring substrate, electronic device and manufacturing method thereof

US10276515B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10276515-B2
Application numberUS-201815933539-A
CountryUS
Kind codeB2
Filing dateMar 23, 2018
Priority dateSep 25, 2015
Publication dateApr 30, 2019
Grant dateApr 30, 2019

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A wiring substrate comprising: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer, wherein the second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and wherein an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer. 2. The wiring substrate according to claim 1 , wherein the second wiring layer and the via conductor further include a metal layer arranged to surround the first sintered metal layer. 3. The wiring substrate according to claim 1 , wherein the first sintered metal layer in the via conductor includes a first curved part forming a continuous corner part between a bottom part and a side wall part of the via conductor, and a curvature radius of the first curved part is ¼ or more of a height of the via conductor. 4. The wiring substrate according to claim 2 , wherein the first sintered metal layer in the via conductor includes a first curved part forming a continuous corner part between a bottom part and a side wall part, and a curvature radius of the first curved part is ¼ or more of a height of the via conductor. 5. The wiring substrate according to claim 1 , wherein the second wiring layer includes a wiring part and a land part, the land part is wider than the via conductor in a cross sectional view in a thickness direction, and the land part is electrically connected to the via conductor, and wherein the first sintered metal layer in the land part includes a second curved part forming a continuous corner part between a bottom part and a side wall part of the land part, and a curvature radius of the second curved part is ¼ or more of a height of the land part. 6. The wiring substrate according to claim 2 , wherein the second wiring layer includes a wiring part and a land part, the land part is wider than the via conductor in a cross sectional view in a thickness direction, and the land part is electrically connected to the via conductor, and wherein the first sintered metal layer in the land part includes a second curved part forming a continuous corner part between a bottom part and a side wall part of the land part, and a curvature radius of the second curved part is ¼ or more of a height of the land part. 7. The wiring substrate according to claim 3 , wherein the second wiring layer includes a wiring part and a land part, the land part is wider than the via conductor in a cross sectional view in a thickness direction, and the land part is electrically connected to the via conductor, and wherein the first sintered metal layer in the land part includes a second curved part forming a continuous corner part between a bottom part and a side wall part of the land part, and a curvature radius of the second curved part is ¼ or more of a height of the land part. 8. The wiring substrate according to claim 4 , wherein the second wiring layer includes a wiring part and a land part, the land part is wider than the via conductor in a cross sectional view in a thickness direction, and the land part is electrically connected to the via conductor, and wherein the first sintered metal layer in the land part includes a second curved part forming a continuous corner part between a bottom part and a side wall part of the land part, and a curvature radius of the second curved part is ¼ or more of a height of the land part.

Assignees

Inventors

Classifications

  • comprising multiple insulating layers · CPC title

  • Applying pastes or inks, e.g. screen printing (H10W70/095 takes precedence) · CPC title

  • Conductive materials thereof · CPC title

  • Shapes or dispositions of interconnections · CPC title

  • Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

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Frequently asked questions

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What does patent US10276515B2 cover?
Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second si…
Who is the assignee on this patent?
Dainippon Printing Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/05. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 30 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).