Integrated circuit with backside structures to reduce substrate warp

Patent metadata

Field	Value
Publication number	US-10276513-B2
Application number	US-201715589195-A
Country	US
Kind code	B2
Filing date	May 8, 2017
Priority date	Jun 25, 2013
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.

First claim

The invention claimed is:

1. A method, comprising:
receiving a semiconductor wafer having a front side and a back side;
forming a front side structure on the front side of the semiconductor wafer, the front side structure exerting a first wafer-bowing stress tending to bow the semiconductor wafer;
measuring a first amount of bow of the semiconductor wafer after the front side structure has been formed;
determining a thickness for one or more stress-inducing films to be formed based on the measured first amount of bow; and
forming the one or more stress-inducing films with the determined thickness on the back side of the semiconductor wafer and/or on the front side of the semiconductor wafer to reduce the first amount of bow in the semiconductor wafer.

2. The method of claim 1 , wherein the forming of the one or more stress-inducing films exerts a second wafer-bowing stress that offsets the first wafer-bowing stress, thereby leaving a second amount of bow in the semiconductor wafer; and further comprising:
forming an additional layer configured to exert an additional wafer-bowing stress on the semiconductor wafer to compensate for a difference between the first wafer-bowing stress and the second wafer-bowing stress and to reduce the second amount of bow.

3. The method of claim 2 , wherein the additional layer is formed on the back side of the semiconductor wafer and wherein there is no layer on the front side of the semiconductor wafer which has the same thickness and material composition as the additional layer.

4. The method of claim 1 , wherein the forming of the front side structure comprises:
forming front side dielectric and front side conductive layers which are stacked over one another and configured to exert stress on the front side of the semiconductor wafer.

5. The method of claim 4 , wherein the forming of the one or more stress-inducing films with the determined thickness occurs on the back side of the semiconductor wafer and comprises:
forming back side dielectric and back side conductive layers which correspond in a one-to-one manner to the front side dielectric and front side conductive layers and which have material compositions corresponding to those of the front side dielectric and front side conductive layers, respectively.

6. The method of claim 4 , wherein the front side dielectric and front side conductive layers are disposed in trenches extending into the front side of the semiconductor wafer.

7. The method of claim 6 , wherein the back side dielectric and back side conductive layers are disposed in trenches extending into the back side of the semiconductor wafer.

8. The method of claim 7 , wherein the trenches extending into the back side of the semiconductor wafer have different depths from the trenches extending into the front side of the semiconductor wafer.

9. The method of claim 6 , wherein the front side dielectric and front side conductive layers comprise:
a first front side dielectric layer which directly abuts and lines sidewalls and bottom surfaces of the trenches and which extends continuously over the front side of the semiconductor wafer between the trenches;
a first front side conductive layer extending continuously over the first front side dielectric layer, the first front side conductive layer disposed in the trenches and over the front side of the semiconductor wafer between the trenches.

10. A method of manufacturing an integrated circuit device, comprising:
providing a first semiconductor wafer;
forming first structures on a front side of the first semiconductor wafer, the first structures including deep trench capacitors; and
forming compressive stress-inducing second structures on a back side of the first semiconductor wafer, wherein forming the compressive stress-inducing second structures on the back side of the first semiconductor wafer includes forming trenches in the first semiconductor wafer and then filling the trenches with tensile material.

11. The method of claim 10 , wherein a first of the front and back side structures to be formed cause the first semiconductor wafer to warp in one direction and a second of the front and back side structures to be formed reduces the warp by at least half.

12. The method of claim 10 , wherein:
forming the deep trench capacitors comprises lithography using a photolithographic mask; and
forming the second structures on the back side comprises etching trenches in the back side of the first semiconductor wafer using the photolithographic mask.

13. The method of claim 10 , wherein a dimension of the trenches on the back side of the first semiconductor wafer are selected to cause the stresses on the back side of the first semiconductor wafer to balance those on the front side.

14. The method of claim 10 , wherein forming the compressive stress-inducing structures on the back side of the first semiconductor wafer includes forming one or more tensile films that collectively have a thickness greater than 1 μm.

15. The method of claim 10 , further comprising:
forming one or more compressive films over the structures on the front side of the first semiconductor wafer;
wherein a thickness for the compressive films is selected to balance the stresses on the front side and the back side of the first semiconductor wafer.

16. The method of claim 10 , further comprising connecting the first semiconductor wafer to a second semiconductor wafer comprising a high voltage or high power integrated circuit to form a 3D-IC.

17. The method of claim 10 , further comprising connecting circuits of the first semiconductor wafer to circuits of a second semiconductor wafer through wafer-to-wafer bonding.

18. A method of manufacturing an integrated circuit device, comprising:
providing a semiconductor wafer;
forming first structures on a front side of the semiconductor wafer, the first structures including deep trench capacitors;
measuring a first amount of bow of the semiconductor wafer after the first structures have been formed;
determining a thickness for one or more stress-inducing films to be formed based on the measured first amount of bow; and
forming the one or more stress-inducing films with the determined thickness on a back side of the semiconductor wafer and/or on the front side of the semiconductor wafer to reduce the first amount of bow in the semiconductor wafer.

19. The method of claim 18 , wherein forming the one or more stress-inducing films reduces the first amount of bow by at least half.

20. The method of claim 18 , wherein the one or more stress-inducing films on the back side of the semiconductor wafer are formed within back side trenches, wherein dimensions of the back side trenches are selected to induce stresses on the back side of the semiconductor wafer to reduce the first amount of bow.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chih-Ming
• Wang Szu-Yu
• Yu Chung-Yi

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title