Preclean and deposition methodology for superconductor interconnects

Patent metadata

Field	Value
Publication number	US-10276504-B2
Application number	US-201715597565-A
Country	US
Kind code	B2
Filing date	May 17, 2017
Priority date	May 17, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A method is provided of forming a superconductor interconnect structure. The method comprises forming a dielectric layer overlying a substrate, forming an interconnect opening in the dielectric layer, and moving the substrate to a deposition chamber. The method further comprises performing a cleaning process on the top surface of the dielectric layer and in the interconnect opening while in the deposition chamber, and depositing a superconducting metal in the interconnect opening while in the deposition chamber to form a superconducting element in the superconductor interconnect structure.

First claim

What is claimed is:

1. A method of forming a superconductor interconnect structure, the method comprising:
forming a dielectric layer overlying a substrate;
forming an interconnect opening in the dielectric layer;
moving the substrate to a deposition chamber, wherein the deposition chamber is a physical vapor deposition (PVD) chamber;
performing a cleaning process on the top surface of the dielectric layer and in the interconnect opening while in the deposition chamber, wherein the PVD chamber is configured in an Inductively Coupled Plasma (ICP) mode; and
depositing a superconducting metal in the interconnect opening while in the deposition chamber to form a superconducting element in the superconductor interconnect structure wherein the PVD chamber is configured in a Self Ionized Plasma (SIP) mode.

2. The method of claim 1 , wherein the superconductor interconnect element is formed from niobium that resides as a target slab material in the deposition chamber.

3. The method of claim 1 , further comprising performing a chemical mechanical polish (CMP) to align a top surface of the superconductor interconnect element with a top surface of the first dielectric layer.

4. The method of claim 1 , wherein the dielectric layer is a second dielectric layer that overlays a first dielectric layer having a first conductive line, and the interconnect opening is a dual damascene structure, such that the superconductor interconnect element is both a second conductive line and a contact that connects the first conductive line to the second conductive line through the second dielectric layer.

5. The method of claim 1 , wherein the cleaning process is a sputter etch process.

6. The method of claim 5 , wherein the cleaning process is an argon sputter etch process.

7. The method of claim 1 , wherein the superconductor interconnect structure is part of a wafer that resides on a temperature control chuck during performing of the cleaning process and the depositing of a superconducting metal.

8. The method of claim 7 , wherein the cleaning process comprises:
injecting Argon (AR) into the deposition chamber;
setting a DC power applied to a slab of superconducting target material to about 500 Watts to about 1000 Watts to provide minimal deposition of the superconducting target material;
setting AC power applied to the wafer to be about 100 Watts to about 500 Watts; and
setting the RF Coil to about 1000 Watts to about 2400 Watts to increase Argon (AR) ionization and increase etch rate on the oxides residing in the interconnect opening to overcome the deposition rate of the superconducting target material.

9. The method of claim 7 , wherein the depositing a superconducting metal process comprises:
setting DC power applied to a slab of superconducting target material to about 15000 Watts to about 20000 Watts to be high enough to sputter target material onto the dielectric layer and into the interconnect opening; and
setting AC bias applied to the wafer to be about 0 Watts to about 100 Watts to be low enough to provide a linear directionality to the ionized metal.

10. A method of forming a superconductor dual damascene structure, the method comprising:
forming a first dielectric layer overlying a substrate;
forming a first superconducting element in the first dielectric layer;
forming a second dielectric layer over the first dielectric layer and the first superconducting element;
etching a contact opening in the second dielectric layer that extends to and exposes the first superconducting element in the first dielectric layer;
etching a conductive line opening in the second dielectric layer that overlies the contact opening to form a dual damascene opening;
moving the structure to a deposition chamber;
performing a cleaning process on the top surface of the second dielectric layer and in the dual damascene opening while in the deposition chamber;
depositing a superconducting metal in the dual damascene opening while in the deposition chamber to form a dual damascene structure comprised of a contact and a second conductive line overlying and coupled to the contact, such that the contact connects the first conductive line to the second conductive line through the second dielectric layer.

11. The method of claim 10 , wherein the dual damascene structure is formed from niobium that resides as a target slab material coupled to the deposition chamber.

12. The method of claim 10 , further comprising performing a chemical mechanical polish (CMP) to align a top surface of the second conductive line with a top surface of the second dielectric layer.

13. The method of claim 10 , wherein the deposition chamber is a physical vapor deposition (PVD) chamber that is configured in an Inductively Coupled Plasma (ICP) mode during the cleaning process and that is configured in a Self Ionized Plasma (SIP) mode during the depositing a superconducting metal.

14. The method of claim 10 , wherein the superconductor interconnect structure is part of a wafer that resides on a temperature control chuck while in the deposition chamber.

15. The method of claim 14 , wherein the cleaning process comprises:
injecting Argon (AR) into the deposition chamber;
setting DC power applied to a slab of superconducting target material to about 500 Watts to about 1000 Watts to provide minimal deposition of the superconducting target material;
setting AC power applied to the wafer to be about 100 Watts to about 500 Watts;
setting the RF Coil to about 1000 Watts to about 2400 Watts to increase Argon (AR) ionization and the etch rate on the oxides of the second dielectric layer and the dual damascene opening to overcome the deposition rate of the superconducting target material.

16. The method of claim 15 , wherein the depositing a superconducting metal process comprises:
setting DC power applied to the slab of superconducting target material to about 15000 Watts to about 20000 Watts to be high enough to sputter target material into the dual damascene opening; and
setting AC bias applied to the wafer to be about 0 Watts to about 100 Watts to be low enough to provide a linear directionality to the ionized metal flux.

17. A method of forming a superconductor interconnect structure, the method comprising:
forming a dielectric layer overlying a substrate;
forming an interconnect opening in the dielectric layer;
moving the substrate onto a temperature control chuck of a physical vapor deposition (PVD) chamber, which contains a slab of superconducting niobium target material disposed on a top portion of the PVD;
injecting Argon (AR) into the deposition chamber;
setting the PVD chamber to an Inductively Coupled Plasma (ICP) mode resulting in an argon sputter etch on the top surface of the dielectric layer and the interconnect opening; and
setting the PVD chamber to a Self Ionized Plasma (SIP) mode resulting in the depositing of superconducting niobium in the interconnect opening from the slab of superconducting niobium target material to form a superconducting element in the dielectric layer.

18. The method of claim 17 , wherein setting the PVD chamber to an ICP mode comprises:
setting DC power applied to a slab of superconducting target material to about 500 Watts to about 1000 Watts to provide minimal deposition of the superconducting target material;
setting AC power applied to the substrate to be about 100 Watts to about 500 Watts; and
setting the RF Coil to about 1000 Watts to about 2400 Watts to increase Argon (AR) ionization and increase etch rate on the oxides on the dielectric layer and

Assignees

• Luu Vivien
• Kirby Christopher F
• Wagner Brian
• Rennie Michael
• Northrop Grumman Systems Corp

Inventors

• Luu Vivien
• Kirby Christopher F
• Wagner Brian
• Rennie Michael

Classifications

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title