Metal gate structure cutting process

Patent metadata

Field	Value
Publication number	US-10269787-B2
Application number	US-201715809898-A
Country	US
Kind code	B2
Filing date	Nov 10, 2017
Priority date	Jun 29, 2017
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor device structure, the method comprising
forming a metal gate structure over a first fin structure and a second fin structure disposed on a substrate, wherein an interlayer dielectric (ILD) layer is formed between the first and the second fin structures;
performing an ILD recess etching process to selectively form a recess in the ILD layer;
forming a dielectric structure in the recess;
performing a metal gate structure cutting process to form a line-cut that divides the metal gate structure into sub-metal gate structures, the line-cut further being formed at least partially in the dielectric structure; and
forming an isolation structure in the line-cut.

2. The method of claim 1 , wherein performing the metal gate structure cutting process further comprises:
removing a portion of the dielectric structure.

3. The method of claim 1 , wherein forming the dielectric structure further comprises:
forming a conformal liner layer along a sidewall of the ILD layer and a bottom surface of the recess.

4. The method of claim 1 , wherein forming a dielectric structure in the recess further comprises:
fully filling the recess with the dielectric structure.

5. The method of claim 1 , wherein the dielectric structure has a first side interfaced with the ILD layer and a second side interfaced with the isolation structure.

6. The method of claim 1 , wherein the dielectric structure is fabricated from a first material different from a second material of the isolation structure.

7. The method of claim 6 , wherein the first material of the dielectric structure is different from a third material of the ILD layer.

8. A method for manufacturing semiconductor device structure, the method comprising:
etching an interlayer dielectric (ILD) layer disposed on a substrate to form a recess in the ILD layer, wherein the recess is formed among a plurality of metal gate structures formed in the ILD layer;
after etching the ILD layer, forming a dielectric structure in the recess;
after forming the dielectric structure, forming a line-cut in the plurality of metal gate structures to divide the metal gate structures into sub-metal gate structures, the line-cut being formed at least partially in the dielectric structure; and
filling the line-cut with an isolation structure.

9. The method of claim 8 , wherein forming the line-cut in the metal gate structures further comprises:
removing a portion of the dielectric structure from the substrate.

10. The method of claim 8 , wherein forming the dielectric structure further comprises:
forming a conformal liner layer along a sidewall of the ILD layer and a bottom surface of the recess.

11. The method of claim 8 , wherein forming the dielectric structure further comprises:
fully filling the recess with the dielectric structure.

12. The method of claim 8 , wherein the dielectric structure fully or partially circumscribes a perimeter of the isolation structure.

13. A method for manufacturing a semiconductor device structure, the method comprising
forming a first recess in a first dielectric layer, the first recess exposing opposing sidewalls of a first gate structure, the first gate structure extending over a first fin structure and a second fin structure, the first recess being interposed between the first fin structure and the second fin structure;
forming a second dielectric layer in the first recess;
removing a portion of the second dielectric layer and a portion the first gate structure to form a second recess, wherein the second recess separates the first gate structure into a second gate structure and a third gate structure; and
forming a third dielectric layer in the second recess, wherein the third dielectric layer is interposed between the second gate structure and the third gate structure.

14. The method of claim 13 , wherein, after removing the portion of the second dielectric layer, the second dielectric layer extends along portions of the sidewalls of the second recess.

15. The method of claim 13 , wherein removing the portion of the first gate structure comprises removing a portion of an isolation region underlying the first gate structure.

16. The method of claim 13 , wherein, after forming the third dielectric layer, the second dielectric layer is interposed between a bottom of the third dielectric layer and the first dielectric layer.

17. The method of claim 13 , wherein, after forming the third dielectric layer, portions of the second dielectric layer on a first side of the first gate structure is completely separated from portions of the second dielectric layer on a second side of the first gate structure.

18. The method of claim 13 , wherein the second dielectric layer and the third dielectric layer are interposed between the first fin structure and the second fin structure.

19. The method of claim 13 , wherein removing the portion of the second dielectric layer completely removes the second dielectric layer along a bottom of the second recess.

20. The method of claim 19 , wherein the second recess extends into the first fin structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Shiang-Bau
• Chang Ming-Ching
• Ku Shu-Yuan
• Chen Ryan Chia-Jen

Classifications

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title