Gate cut with high selectivity to preserve interlevel dielectric layer

Patent metadata

Field	Value
Publication number	US-9659786-B2
Application number	US-201514799297-A
Country	US
Kind code	B2
Filing date	Jul 14, 2015
Priority date	Jul 14, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.

First claim

The invention claimed is:

1. A method for preserving interlevel dielectric in a gate cut region, comprising:
recessing a dielectric fill to expose a cap layer of gate structures formed in a device region and in a cut region;
forming a liner in a recess on top of the recessed dielectric fill, the liner including a material to provide etch selectivity to protect the dielectric fill;
recessing the gate structures in the cut region to form a gate recess using the liner to protect the dielectric fill from being etched;
removing a gate material from within the gate structure using the liner to protect the dielectric fill from being etched; and
forming a dielectric gap fill to replace the gate material and to fill the gate recess in the cut region.

2. The method as recited in claim 1 , wherein forming the liner includes:
conformally depositing the liner over the gate structures and on the top of the recessed dielectric fill; and
planarizing the liner to remove the liner over the gate structures.

3. The method as recited in claim 1 , wherein forming the liner includes forming the liner from a material that resists etching during recessing the cap layer and removing the gate material.

4. The method as recited in claim 1 , wherein forming the liner includes forming the liner from TiN.

5. The method as recited in claim 1 , wherein recessing the gate structures in the cut region includes patterning a mask layer to protect the device region and etching the cap layer of the gate structure in the cut region.

6. The method as recited in claim 1 , wherein removing the gate material includes removing one of a dummy gate or a gate first structure.

7. The method as recited in claim 1 , wherein forming the dielectric gap fill includes forming the dielectric gap fill between spacers formed in the gate structure.

8. A method for preserving interlevel dielectric in a gate cut region, comprising:
forming gate structures in a device region and a cut region;
forming source and drain regions in the device region;
depositing and planarizing a dielectric fill to fill in gaps between gate structures in the device region and the cut region;
recessing the dielectric fill to expose a cap layer at a top portion of the gate structures;
forming a liner in the recess on top of the recessed dielectric fill, the liner including a material to provide etch selectivity to protect the dielectric fill;
recessing the gate structures in the cut region to form a gate recess using the liner to protect the dielectric fill from being etched;
removing a gate material from within the gate structure using the liner to protect the dielectric fill from being etched; and
forming a dielectric gap fill to replace the gate material and to fill the gate recess in the cut region.

9. The method as recited in claim 8 , wherein forming the liner includes:
conformally depositing the liner over the gate structures and on the top of the recessed dielectric fill; and
planarizing the liner to remove the liner over the gate structures.

10. The method as recited in claim 8 , wherein forming the liner includes forming the liner from a material that resists etching during recessing the cap layer and removing the gate material.

11. The method as recited in claim 8 , wherein forming the liner includes forming the liner from TiN.

12. The method as recited in claim 8 , wherein recessing the gate structures in the cut region includes patterning a mask layer to protect the device region and etching the cap layer of the gate structure in the cut region.

13. The method as recited in claim 8 , wherein removing the gate material includes removing one of a dummy gate or a gate first structure.

14. The method as recited in claim 8 , wherein forming the dielectric gap fill includes forming the dielectric gap fill between spacers formed in the gate structure.

15. A method for preserving interlevel dielectric in a gate cut region, comprising:
forming gate structures in a device region and a cut region, the gate structures including a cap layer and spacer layers and a gate material disposed between the spacer layers;
forming source and drain regions adjacent to the gate structures in the device region;
depositing and planarizing a dielectric fill to fill in gaps between gate structures in the device region and the cut region;
recessing the dielectric fill to expose the cap layer at a top portion of the gate structures;
forming a liner in the recess on top of the recessed dielectric fill by conformally depositing the liner over the gate structures and on the top of the recessed dielectric fill, and planarizing the liner to remove the liner over the gate structures, the liner including a material to provide etch selectivity to protect the dielectric fill;
recessing the gate structures in the cut region to form a gate recess using the liner to protect the dielectric fill from being etched by patterning a mask layer to protect the device region and etching the cap layer of the gate structure in the cut region;
removing the gate material from within the gate structure using the liner to protect the dielectric fill from being etched; and
forming a dielectric gap fill to replace the gate material between the spacers of the gate structures and to fill the gate recess in the cut region.

16. The method as recited in claim 15 , wherein forming the liner includes forming the liner from a material that resists etching during recessing the cap layer and removing the gate material.

17. The method as recited in claim 15 , wherein forming the liner includes forming the liner from TiN.

18. The method as recited in claim 15 , wherein removing the gate material includes removing one of a dummy gate or a gate first structure.

19. The method as recited in claim 15 , wherein forming source and drain regions in the device region includes epitaxially growing the source and drain regions between the gate structures.

20. The method as recited in claim 15 , wherein forming the dielectric gap fill includes depositing the dielectric gap fill and planarizing to remove the dielectric gap fill from a surface of the dielectric fill and to remove the liner.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Greene Andrew M
• Jung Ryan O
• Xie Ruilong

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10D64/01302

  the insulator being formed after the semiconductor body, the semiconductor being silicon · CPC title