Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Patent metadata

Field	Value
Publication number	US-10268518-B2
Application number	US-201815997863-A
Country	US
Kind code	B2
Filing date	Jun 5, 2018
Priority date	May 11, 2016
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.

First claim

What is claimed is:

1. A multi-slice processor comprising:
a plurality of execution slices and a plurality of load/store slices, wherein the multi-slice processor is configured to carry out:
receiving, at a load/store slice, an instruction to be issued; and
responsive to determining a rejection condition for the instruction, maintaining state information for the instruction in the load/store slice.

2. The multi-slice processor of claim 1 , wherein the multi-slice processor is further configured to carry out:
determining that the rejection condition for the instruction has resolved or is pending resolution; and
responsive to determining that the rejection condition for the instruction has resolved or is pending resolution, reissuing the instruction from within the load/store slice.

3. The multi-slice processor of claim 2 , wherein the multi-slice processor is further configured to carry out:
responsive to determining that the rejection condition for the instruction has resolved or is pending resolution, notifying an instruction sequencing unit that the instruction is being reissued.

4. The multi-slice processor of claim 2 , wherein the instruction is a load instruction, and wherein the multi-slice processor is further configured to carry out:
determining an arrival of data for the instruction from a lower tier of memory into a data cache on the load/store slice; and
scheduling the instruction to be issued such that the instruction may provide the data for the instruction to a destination without accessing the data cache.

5. The multi-slice processor of claim 1 , wherein the multi-slice processor is further configured to carry out:
determining that the rejection condition is expected to resolve within a quantity of cycles; and
responsive to determining that the rejection condition is expected to resolve within the quantity of cycles, scheduling the instruction to be issued coincident with a lapse of the quantity of cycles.

6. The multi-slice processor of claim 1 , wherein the load/store slice comprises a load/store access queue and a load reorder queue, and wherein receiving the instruction to be issued comprises:
determining that the instruction is a load instruction; and
providing, from the load/store access queue to the load reorder queue, the instruction.

7. The multi-slice processor of claim 1 , wherein the load/store slice comprises a load/store access queue and a store reorder queue, and wherein receiving the instruction to be issued comprises:
determining that the instruction is a store instruction; and
providing, from the load/store access queue to the store reorder queue, the instruction.

8. An apparatus comprising:
a multi-slice processor and computer memory coupled to the multi-slice processor, wherein the multi-slice processor comprises:
a plurality of execution slices and a plurality of load/store slices, wherein the multi-slice processor is configured to carry out:
receiving, at a load/store slice, an instruction to be issued; and
responsive to determining a rejection condition for the instruction, maintaining state information for the instruction in the load/store slice.

9. The apparatus of claim 8 , wherein the multi-slice processor is further configured to carry out:
determining that the rejection condition for the instruction has resolved or is pending resolution; and
responsive to determining that the rejection condition for the instruction has resolved or is pending resolution, reissuing the instruction from within the load/store slice.

10. The apparatus of claim 9 , wherein the multi-slice processor is further configured to carry out:
responsive to determining that the rejection condition for the instruction has resolved or is pending resolution, notifying an instruction sequencing unit that the instruction is being reissued.

11. The apparatus of claim 10 , wherein the instruction is a load instruction, and wherein the multi-slice processor is further configured to carry out:
determining an arrival of data for the instruction from a lower tier of memory into a data cache on the load/store slice; and
scheduling the instruction to be issued such that the instruction may provide the data for the instruction to a destination without accessing the data cache.

12. The apparatus of claim 8 , wherein the multi-slice processor is further configured to carry out:
determining that the rejection condition is expected to resolve within a quantity of cycles; and
responsive to determining that the rejection condition is expected to resolve within the quantity of cycles, scheduling the instruction to be issued coincident with a lapse of the quantity of cycles.

13. The apparatus of claim 8 , wherein the load/store slice comprises a load/store access queue and a load reorder queue, and wherein receiving the instruction to be issued comprises:
determining that the instruction is a load instruction; and
providing, from the load/store access queue to the load reorder queue, the instruction.

Assignees

• IBM

Inventors

• Chadha Sundeep
• Cordes Robert A
• Hrusecky David A
• Le Hung Q
• Mcglone Elizabeth A

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/3891 Primary

  organised in groups of units sharing resources, e.g. clusters · CPC title

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title