Processor performance improvement for instruction sequences that include barrier instructions

Patent metadata

Field	Value
Publication number	US-8935513-B2
Application number	US-201213369029-A
Country	US
Kind code	B2
Filing date	Feb 8, 2012
Priority date	Feb 8, 2012
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining that the load instruction is resolved based upon receipt of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.

First claim

What is claimed is:

1. A data processing system configured to process an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction, the data processing system comprising:
a cache memory; and
a processor core coupled to the cache memory, wherein the processor core is configured to:
determine that the load instruction is resolved based upon receipt by the processor core of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction;
if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating by the processor core, in response to determining the barrier instruction completed, execution of the subsequent memory access instruction; and
if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing by the processor core, in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.

2. The data processing system of claim 1 , wherein the processor core is further configured to:
insert an entry for the load instruction into a load reorder queue; and
mark the entry in the load reorder queue as resolved in response to determining that the load instruction is resolved.

3. The data processing system of claim 1 , wherein the subsequent memory access instruction is a subsequent load instruction.

4. The data processing system of claim 1 , wherein the subsequent memory access instruction is a subsequent store instruction.

5. The data processing system of claim 1 , further comprising the processor core receiving the good combined response for the read operation corresponding to the load instruction prior to receiving the data for the load instruction.

6. The data processing system of claim 1 , further comprising the processor core receiving the good combined response for the read operation corresponding to the load instruction subsequent to receiving the data for the load instruction.

7. The data processing system of claim 1 , wherein the barrier instruction completes when all load and store instructions prior to the barrier instruction are resolved.

8. A data processing system configured to process an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction, the data processing system comprising:
a level two cache memory; and
a processor core coupled to the cache memory, wherein the processor core is configured to:
determine that the load instruction is resolved based upon receipt by the processor core of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction;
if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating by the processor core, in response to determining the barrier instruction completed, execution of the subsequent memory access instruction; and
if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing by the processor core, in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.

9. The data processing system of claim 8 , wherein the processor core includes a load-store unit that includes a load reorder queue (LRQ) and LRQ resolving logic, and wherein the LRQ resolving logic is configured to:
insert an entry for the load instruction into the LRQ; and
mark the entry in the LRQ as resolved in response to determining that the load instruction is resolved.

10. The data processing system of claim 8 , wherein the subsequent memory access instruction is a subsequent load instruction.

11. The data processing system of claim 8 , wherein the subsequent memory access instruction is a subsequent store instruction.

12. The data processing system of claim 8 , further comprising the processor core receiving the good combined response for the read operation corresponding to the load instruction prior to receiving the data for the load instruction.

13. The data processing system of claim 8 , further comprising the processor core receiving the good combined response for the read operation corresponding to the load instruction subsequent to receiving the data for the load instruction.

Assignees

• Guthrie Guy L
• Starke William J
• Williams Derek E
• IBM

Inventors

• Guthrie Guy L
• Starke William J
• Williams Derek E

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/52 Primary

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/30087 Primary

  Synchronisation or serialisation instructions · CPC title