Semiconductor device

Patent metadata

Field	Value
Publication number	US-10263177-B2
Application number	US-201715814975-A
Country	US
Kind code	B2
Filing date	Nov 16, 2017
Priority date	Dec 28, 2016
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

The vertical Hall element includes: a second conductivity type semiconductor layer formed on a first conductivity type semiconductor substrate; a plurality of high-concentration second conductivity type electrodes formed in a straight line on a surface of the semiconductor layer having substantially the same shape, and spaced at a first interval; a plurality of electrode isolation layers each formed between two electrodes out of the plurality of electrodes to isolate the plurality of electrodes from one another having substantially the same shape, and spaced at a second interval; and a first added layer and a second added layer each formed along the straight line outside of the outermost electrodes, and each having substantially the same structure as that of each electrode isolation layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type; and
a vertical Hall element provided on the semiconductor substrate,
the vertical Hall element comprising:
a semiconductor layer of a second conductivity type formed on the semiconductor substrate;
a plurality of electrodes formed along a straight line on a surface of the semiconductor layer, and each formed from an impurity region of the second conductivity type having a concentration higher than that of the semiconductor layer, the plurality of electrodes having substantially the same shape and being spaced at a first interval;
a plurality of electrode isolation layers each formed between two electrodes out of the plurality of electrodes on the surface of the semiconductor layer, to isolate the plurality of electrodes from one another, the plurality of electrode isolation layers having substantially the same shape and being spaced at a second interval; and
a first added layer and a second added layer each formed along the straight line outside of outermost electrodes among the plurality of electrodes, the first added layer and the second added layer each having substantially the same structure as a structure of each of the plurality of electrode isolation layers,

the first added layer being spaced apart by the second interval from one of the plurality of electrode isolation layers which is adjacent to one of the outermost electrodes,
the second added layer being spaced apart by the second interval from another one of the plurality of electrode isolation layers which is adjacent to another of the outermost electrodes.

2. The semiconductor device according to claim 1 , further comprising an element isolation diffusion layer of the first conductivity type enclosing the vertical Hall element to electrically isolate the vertical Hall element from surroundings.

3. The semiconductor device according to claim 2 , wherein, in a running direction of the straight line, substantially the same distance is set between the first added layer and a first inner side surface of the element isolation diffusion layer that is adjacent to the first added layer, and between the second added layer and a second inner side surface of the element isolation diffusion layer that is adjacent to the second added layer.

4. The semiconductor device according to claim 3 , wherein an interval between one of the outermost electrodes and the first inner side surface of the element isolation diffusion layer and an interval between another of the outermost electrodes and the second inner side surface of the element isolation diffusion layer are each at least as large as the first interval.

5. The semiconductor device according to claim 4 , wherein the plurality of electrode isolation layers, the first added layer, and the second added layer comprise diffusion layers of the first conductivity type.

6. The semiconductor device according to claim 5 , wherein the surface of the semiconductor layer, a surface of the first added layer, and a surface of the second added layer are covered with an insulating film, except for regions in which the plurality of electrodes are formed.

7. The semiconductor device according to claim 4 , wherein a number of the plurality of electrodes is at least four.

8. The semiconductor device according to claim 3 , wherein the plurality of electrode isolation layers, the first added layer, and the second added layer comprise diffusion layers of the first conductivity type.

9. The semiconductor device according to claim 8 , wherein the surface of the semiconductor layer, a surface of the first added layer, and a surface of the second added layer are covered with an insulating film, except for regions in which the plurality of electrodes are formed.

10. The semiconductor device according to claim 3 , wherein a number of the plurality of electrodes is at least four.

11. The semiconductor device according to claim 2 , wherein the plurality of electrode isolation layers, the first added layer, and the second added layer comprise diffusion layers of the first conductivity type.

12. The semiconductor device according to claim 11 , wherein the surface of the semiconductor layer, a surface of the first added layer, and a surface of the second added layer are covered with an insulating film, except for regions in which the plurality of electrodes are formed.

13. The semiconductor device according to claim 2 , wherein the plurality of electrode isolation layers, the first added layer, and the second added layer comprise insulating layers embedded in trenches.

14. The semiconductor device according to claim 2 , wherein a number of the plurality of electrodes is at least four.

15. The semiconductor device according to claim 1 , wherein the plurality of electrode isolation layers, the first added layer, and the second added layer comprise diffusion layers of the first conductivity type.

16. The semiconductor device according to claim 15 , wherein the surface of the semiconductor layer, a surface of the first added layer, and a surface of the second added layer are covered with an insulating film, except for regions in which the plurality of electrodes are formed.

17. The semiconductor device according to claim 1 , wherein the plurality of electrode isolation layers, the first added layer, and the second added layer comprise insulating layers embedded in trenches.

18. The semiconductor device according to claim 1 , wherein a number of the plurality of electrodes is at least four.

Assignees

• Sii Semiconductor Corp
• Ablic Inc

Inventors

• Hioka Takaaki
• Ebihara Mika

Classifications

• H01L43/065 Primary

  Electricity · mapped topic

• H01L43/04

  Electricity · mapped topic

• G01R33/07

  Hall effect devices · CPC title

• H10N52/101 Primary

  Semiconductor Hall-effect devices · CPC title

• H10N52/80

  Constructional details · CPC title