Vertical hall sensors with reduced offset error

Patent metadata

Field	Value
Publication number	US-9543504-B2
Application number	US-201514918704-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Oct 21, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A semiconductor chip for measuring a magnetic field based on the Hall effect. The semiconductor chip comprises an electrically conductive well having a first conductivity type, in a substrate having a second conductivity type. The semiconductor chip comprises at least four well contacts arranged at the surface of the well, and having the first conductivity type. The semiconductor chip comprises a plurality of buffer regions interleaved with the well contacts and having the first conductivity type. The buffer regions are highly conductive and the buffer region dimensions are such that at least part of the current from a well contact transits through one of its neighboring buffer regions.

First claim

The invention claimed is:

1. A semiconductor chip for measuring a magnetic field based on the Hall effect, the semiconductor chip comprising:
an electrically conductive well having a first conductivity type, in a substrate having a second conductivity type,
at least four well contacts arranged at the surface of the well, and having the first conductivity type,
a plurality of buffer regions interleaved with the well contacts such that at least one of the buffer regions and the electrically conductive well are located between neighboring well contacts, wherein the buffer regions have the first conductivity type, and
wherein the buffer regions are highly conductive and wherein the buffer region dimensions are such that at least part of the current from a well contact to another well contact transits through one of its neighboring buffer regions.

2. A semiconductor chip according to claim 1 , wherein regions in between the well contacts and the buffer regions and/or wherein regions outside outer buffer regions or well contacts are filled with oxide.

3. A semiconductor chip according to claim 1 , wherein regions in between the well contacts and the buffer regions and/or regions outside outer buffer regions or well contacts are covered by a thin dielectric layer with a polysilicon layer on top.

4. A semiconductor chip according to claim 1 , the semiconductor chip comprising a buffer region outside each outer well contact, wherein the buffer region outside the outer well contacts is having the first conductivity type and is highly conductive, and wherein the buffer region outside each of the outer well contacts is at least as wide as the other buffer regions and wherein the two buffer regions outside each of the outer well contacts are electrically connected together on a floating potential.

5. A semiconductor chip according to claim 1 , the semiconductor chip comprising at least 6 well contacts.

6. A semiconductor chip according to claim 1 , wherein a distance between a center of a well contact and a closest edge of a neighboring buffer region is between 1.5 μm and 2 μm for the inner contacts.

7. A semiconductor chip according to claim 1 , wherein the buffer regions are extending to the same depth into the electrically conductive well as the well contacts.

8. A semiconductor chip according to claim 1 , wherein the buffer regions have a width between the width of the well contacts and twice the depth of the electrically conductive well.

9. A semiconductor chip according to claim 1 , wherein the buffer regions neighboring outer well contacts form one entire buffer region surrounding the outer well contact.

10. A semiconductor chip according to claim 9 , wherein a distance between a nearest edge of a surrounding buffer region and a center of the nearest well contact equals a distance between a center of a well contact and a closest edge of a neighboring buffer region, or 0.1 μm or less smaller.

11. A semiconductor chip according to claim 1 , wherein the well contacts are extended using well contact extensions having the first conductivity type.

12. A method for manufacturing a semiconductor chip for measuring a magnetic field based on the Hall effect, wherein applying well contacts and applying buffer regions involves the same processing step or processing steps.

13. A method for manufacturing a semiconductor chip according to claim 12 , wherein the method comprises the following steps:
applying shallow trench isolation,
applying a first conductivity type implant on the regions not covered by the shallow trench isolation.

14. A method for manufacturing a semiconductor chip according to claim 12 , wherein the method comprises the following steps:
applying a thin dielectric layer,
applying polysilicon over the dielectric layer,
etching away the dielectric layer and the polysilicon where the well contacts and the buffer regions will later be formed, and
applying a first conductivity type implant on the regions not covered by the polysilicon layer.

Assignees

• Melexis Technologies Nv
• X-Fab Semiconductor Foundries Ag

Inventors

• Schott Christian
• Hofmann Peter

Classifications

• H01L43/04

  Electricity · mapped topic

• H01L43/065 Primary

  Electricity · mapped topic

• G01R33/07 Primary

  Hall effect devices · CPC title

• G01R33/077

  Vertical Hall-effect devices · CPC title

• H01L43/14

  Electricity · mapped topic