RGBZ pixel unit cell with first and second Z transfer gates

Patent metadata

Field	Value
Publication number	US-10263022-B2
Application number	US-201715655108-A
Country	US
Kind code	B2
Filing date	Jul 20, 2017
Priority date	Dec 22, 2014
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

An image sensor is described having a pixel array. The pixel array has a unit cell that includes visible light photodiodes and an infra-red photodiode. The visible light photodiodes and the infra-red photodiode are coupled to a particular column of the pixel array. The unit cell has a first capacitor coupled to the visible light photodiodes to store charge from each of the visible-light photodiodes. The unit cell has a readout circuit to provide the first capacitor's voltage on the particular column. The unit cell has a second capacitor that is coupled to the infra-red photodiode through a first transfer gate transistor to receive charge from the infra-red photodiode during a time-of-flight exposure. The first capacitor is coupled to the infra-red photodiode through a second transfer gate transistor to receive charge from the infra-red photodiode during the time-of-flight exposure.

First claim

The invention claimed is:

1. A method, comprising:
transferring first charge from a first photodiode that has received visible light of a first type into a storage capacitor and reading out a first voltage of the storage capacitor at a pixel array column;
transferring second charge from a second photodiode that has received visible light of a second type into the storage capacitor and reading out a second voltage of the storage capacitor at the pixel array column;
transferring third charge from a third photodiode that has received visible light of a third type into the storage capacitor and reading out a third voltage of the storage capacitor at the pixel array column;
transferring fourth charge from a fourth photodiode that has received infra red light during a time-of-flight exposure into a second storage capacitor and reading out a fourth voltage of the second storage capacitor at the pixel array column; and,
transferring fifth charge from the fourth photodiode that has received infra red light during the time-of-flight exposure into the first storage capacitor and reading out a fifth voltage of the first storage capacitor at the pixel array column.

2. The method of claim 1 further comprising transferring said fourth charge with a first clock signal and transferring said fifth charge with a second clock signal.

3. The method of claim 2 wherein said first and second clock signals are 180° out of phase with each other.

4. The method of claim 1 further comprising permitting sixth charge from any of said first, second and third photo-diodes to flow into a supply node during said time-of-flight exposure time.

5. The method of claim 1 further comprising permitting sixth charge to be transferred from said fourth photo-diode into a supply node while any of said first, second and third photodiodes are accumulating charge during a visible light exposure process.

6. The method of claim 1 further comprising permitting sixth charge to be transferred from said fourth photo-diode into a supply node while sixth charge from any of said first, second and third photodiodes is being readout from said first capacitor.

7. The method of claim 1 further comprising clearing said first, second and third voltages from said first capacitor and clearing said fourth voltage from said second capacitor with a same reset transistor.

8. An apparatus comprising:
a first storage capacitor;
a first photodiode that is configured to receive visible light of a first type and to transfer a first charge into the first storage capacitor
a second photodiode that is configured to receive visible light of a second type and to transfer a second charge into the first storage capacitor;
a third photodiode that is configured to receive visible light of a third type and to transfer a third charge into the first storage capacitor; and
a fourth photodiode that is configured to receive infrared light during a time-of-flight exposure, to transfer a fourth charge into the second storage capacitor, and to transfer a fifth charge into the first storage capacitor,
wherein a first voltage is read out of the first storage capacitor at a pixel array column after the first charge has been transferred into the first storage capacitor,
wherein a second voltage is read out of the first storage capacitor at the pixel array column after the second charge has been transferred into the first storage capacitor,
wherein a third voltage is read out of the first storage capacitor at the pixel array column after the third charge has been transferred into the first storage capacitor,
wherein a fourth voltage is read out of the second storage capacitor at the pixel array column after the fourth charge has been transferred into the second storage capacitor, and
wherein a fifth voltage is read out of the first storage capacitor at the pixel array column after the fifth charge has been transferred into the first storage capacitor.

9. The apparatus of claim 8 , wherein fourth charge is transferred with a first clock signal and the fifth charge is transferred with a second clock signal.

10. The apparatus of claim 9 , wherein the first and second clock signals are 180° out of phase with each other.

11. The apparatus of claim 8 , wherein a sixth charge is permitted to flow from any of the first, second and third photodiodes into a supply node during the time-of-flight exposure time.

12. The apparatus of claim 8 , wherein a sixth charge is permitted to be transferred from the fourth photodiode into a supply node while any of the first, second and third photodiodes are accumulating charge during a visible light exposure process.

13. The apparatus of claim 8 , wherein a sixth charge is permitted to be transferred from said fourth photodiode into a supply node while the sixth charge from any of the first, second and third photodiodes is being read out from the first storage capacitor.

14. The apparatus of claim 8 wherein the first, second and third voltages are cleared from the first storage capacitor and the fourth voltage is cleared from the second capacitor with a same reset transistor.

Assignees

• Google Llc

Inventors

• Wan Chung Chun
• Fowler Boyd Albert

Classifications

• H04N23/11

  for generating image signals from visible and infrared light wavelengths · CPC title

• H04N25/705

  Pixels for depth measurement, e.g. RGBZ · CPC title

• H04N23/57

  Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices · CPC title

• H04N25/134

  based on three different wavelength filter elements · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title