Semiconductor device and semiconductor package

Patent metadata

Field	Value
Publication number	US-10256203-B2
Application number	US-201715662261-A
Country	US
Kind code	B2
Filing date	Jul 27, 2017
Priority date	Jul 27, 2017
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

First claim

What is claimed is:

1. A semiconductor device comprising:
a die, comprising a plurality of first pads and a plurality of second pads;
a passivation layer, disposed on the die;
a plurality of first electrical conductive vias and a plurality of second electrical conductive vias, extending through the passivation layer and contacting the first pads and the second pads respectively;
a plurality of thermal conductive vias, disposed over the passivation layer, wherein each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias; and
a connecting pattern, disposed on the passivation layer and connecting the thermal conductive vias and the first electrical conductive vias, wherein the thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

2. The semiconductor device as claimed in claim 1 , wherein the first electrical conductive vias are disposed right above the first pads respectively and the second electrical conductive vias are disposed right above the second vias respectively.

3. The semiconductor device as claimed in claim 1 , wherein the connecting pattern surrounds a region of the passivation layer to connect the electrical conductive vias and at least a set of the thermal conductive vias.

4. The semiconductor device as claimed in claim 1 , wherein the connecting pattern comprises:
a first connecting pattern, surrounding a region of the passivation layer to connect the first electrical conductive vias; and
a second connecting pattern, connecting the first electrical conductive vias and the thermal conductive vias, wherein the thermal conductive vias are disposed within the region and surrounded by the electrical conductive vias.

5. The semiconductor device as claimed in claim 1 , wherein the connecting pattern comprises:
a first connecting pattern, surrounding a region of the passivation layer to connect the first electrical conductive vias and a first set of the thermal conductive vias; and
a second connecting pattern, connecting the first electrical conductive vias and a second set of the thermal conductive vias, wherein the second set of the thermal conductive vias are disposed within the region surrounded by the first electrical conductive vias and the first set of the thermal conductive vias.

6. The semiconductor device as claimed in claim 1 , wherein the connecting pattern comprises:
a first connecting pattern, surrounding a region of the passivation layer to connect the first electrical conductive vias and a first set of the thermal conductive vias; and
a second connecting pattern, connecting the first connecting pattern and a second set of the thermal conductive vias, wherein the second set of the thermal conductive vias are surrounded by the first electrical conductive vias and the first set of the thermal conductive vias.

7. The semiconductor device as claimed in claim 1 , further comprising a plurality of ground vias isolated from the first electrical conductive vias and the thermal conductive vias, and contacting a plurality of ground pads of the die, wherein the first pads are a plurality of power pads of the die and the second pads are a plurality of signal pads of the die.

8. A semiconductor device, comprising:
a die, comprising a plurality of first pads and a plurality of second pads;
a passivation layer, disposed on the die and exposing the first pads and the second pads;
a conductive frame, disposed on the passivation layer and comprising a plurality of first vias penetrating the passivation layer to contact the first pads respectively and a plurality of second vias entirely disposed on top of the passivation layer and connected to the first pads through the conductive frame; and
a plurality of third vias penetrating the passivation layer to contact the second pads respectively.

9. The semiconductor device as claimed in claim 8 , wherein the first vias are disposed right above the first pads respectively, and the third vias are disposed right above the second pads respectively.

10. The semiconductor device as claimed in claim 8 , wherein the conductive frame surrounding a region of the passivation layer.

11. The semiconductor device as claimed in claim 8 , wherein the conductive frame surrounding a region of the passivation layer to connect the first vias and extends toward a center of the region to connect the second vias.

12. The semiconductor device as claimed in claim 8 , wherein the conductive frame surrounding a region of the passivation layer to connect the first vias and a first set of the second vias and extends toward a center of the region to connect a second set of the second vias.

13. The semiconductor device as claimed in claim 8 , further comprising a plurality of fourth vias isolated from the conductive frame and contacting a plurality of ground pads of the die, wherein the first pads are a plurality of power pads of the die, and the second pads are a plurality of signal pads of the die.

14. A semiconductor package, comprising:
a molded semiconductor device comprising a semiconductor device and a molding compound encapsulating the semiconductor device, the semiconductor device comprising:
a die, comprising a plurality of first pads and a plurality of second
a passivation layer, disposed on the die and exposing the first pads and the second pads;
a conductive frame, disposed on the passivation layer and comprising a plurality of first vias penetrating the passivation layer to contact the first pads respectively and a plurality of second vias disposed on top of the passivation layer and connected to the first pads through the conductive frame; and
a plurality of third vias penetrating the passivation layer to contact the second pads; and

a redistribution structure, disposed on the molded semiconductor device and comprising a plurality of first redistribution vias, wherein a first set of the first redistribution vias connect the first vias and a second set of the first redistribution vias connect the second vias.

15. The semiconductor package as claimed in claim 14 , wherein the first vias are disposed right above the first pads respectively, and the second vias are disposed right above the second pads respectively.

16. The semiconductor package as claimed in claim 14 , wherein the conductive frame surrounds a region of the passivation layer.

17. The semiconductor package as claimed in claim 14 , wherein the conductive frame surrounds a region of the passivation layer to connect the first vias and extends toward a center of the region to connect the second vias.

18. The semiconductor package as claimed in claim 14 , wherein the conductive frame surrounds a region of the passivation layer to connect the first vias and a first set of the second vias and extends toward a center of the region to connect a second set of the second vias.

19. The semiconductor package as claimed in claim 14 , wherein the semiconductor device further comprising a plurality of fourth vias isolated from the conductive frame, and contacting a plurality of ground pads of the die, wherein the first pads are a plurality of power pads of the die, and the second pads are a plurality of signal pads of the die.

20. The semiconductor package as claimed in claim 14 , wherein the redistribution structure further comprises:
a first dielectric layer, disposed on the molded semiconductor device, wherein the first redistribution vias penetrate the first dielectric layer;
a first redistribut

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Lipu Kris
• Pu Han-Ping
• Pan Hsin-Yu
• Hsu Sen-Kuei

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/07351

  characterised by changes in properties of the die-attach connectors during connecting · CPC title

• H10W72/967

  Multiple bond pads having different functions · CPC title