Semiconductor package, semiconductor device using the same and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9761534-B2
Application number	US-201615162760-A
Country	US
Kind code	B2
Filing date	May 24, 2016
Priority date	Sep 21, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a package substrate, comprises:
a first conductive layer;
a first pillar layer formed on the first conductive layer;
a first package body encapsulating the first conductive layer and the first pillar layer; and
a second conductive layer electrically connecting to the first pillar layer;
a first electronic component disposed above the second conductive layer of the package substrate;
a second package body encapsulating the first electronic component and the second conductive layer;
a third conductive layer formed on the first package body;
a third pillar layer connecting the third conductive layer to the second conductive layer; and
a third package body encapsulating the third pillar layer and the third conductive layer;
wherein the second conductive layer is formed on the third package body.

2. The semiconductor package as claimed in claim 1 , wherein the first package body is molding compound.

3. The semiconductor package as claimed in claim 1 , further comprises:
a second pillar layer formed on the second conductive layer;
wherein the second package body further encapsulates the second pillar layer.

4. The semiconductor package as claimed in claim 1 , wherein the third package body is molding compound.

5. The semiconductor package as claimed in claim 1 , wherein the first conductive layer has a first lower surface, the first package body has a second lower surface, the first lower surface is exposed form the second lower surface, and the semiconductor package further comprises:
a second electronic component disposed on the first lower surface of the first conductive layer.

6. The semiconductor package as claimed in claim 1 , further comprises:
an interposer disposed on the second package body and electrically connecting to the package substrate.

7. The semiconductor package as claimed in claim 1 , further comprises:
a fourth conductive layer; and
a second pillar layer connecting the fourth conductive layer to the second conductive layer;
wherein the second package body encapsulates the second pillar layer and the fourth conductive layer.

8. The semiconductor package as claimed in claim 1 , wherein the first pillar layer has a first upper surface, the first package body has a second upper surface, and the first upper surface is aligned with the second upper surface.

9. The semiconductor package as claimed in claim 1 , wherein the first conductive layer has a first lower surface, the first package body has a second lower surface, and the first lower surface is aligned with the second lower surface.

10. A semiconductor device, comprising:
a semiconductor package, comprising:
a package substrate, comprises:
a first conductive layer;
a first pillar layer formed on the first conductive layer;
a first package body encapsulating the first conductive layer and the first pillar layer; and
a second conductive layer electrically connecting to the first pillar layer;
a first electronic component disposed above the second conductive layer of the package substrate;
a second package body encapsulating the first electronic component and the second conductive layer;
a second pillar layer formed on the second conductive layer of the semiconductor package; and
a third electronic component disposed above the second package body and electrically connecting to the package substrate through the second pillar layer;
wherein the second package body further encapsulates the second pillar layer;
a third conductive layer formed on the first package body;
a third pillar layer connecting the third conductive layer to the second conductive layer; and
a third package body encapsulating the third pillar layer and the third package body;
wherein the second conductive layer is formed on the third package body.

11. The semiconductor device as claimed in claim 10 , wherein the third package body is molding compound.

12. The semiconductor device as claimed in claim 10 , wherein the first conductive layer has a first lower surface, the first package body has a second lower surface, the first lower surface is exposed form the second lower surface, and the semiconductor package further comprises:
a second electronic component disposed on the first lower surface of the first conductive layer.

13. The semiconductor device as claimed in claim 10 , further comprises:
an interposer disposed on the second package body and electrically connecting to the package substrate through the second pillar layer.

14. The semiconductor device as claimed in claim 10 , further comprises:
a fourth conductive layer;
wherein the second pillar layer connects the fourth conductive layer to the second conductive layer, and the second package body encapsulates the second pillar layer and the fourth conductive layer.

15. The semiconductor device as claimed in claim 10 , wherein the first package body is molding compound.

16. The semiconductor device as claimed in claim 10 , wherein the first pillar layer has a first upper surface, the first package body has a second upper surface, and the first upper surface is aligned with the second upper surface.

17. The semiconductor device as claimed in claim 10 , wherein the first conductive layer has a first lower surface, the first package body has a second lower surface, and the first lower surface is aligned with the second lower surface.

18. A semiconductor device, comprising:
a semiconductor package, comprising:
a package substrate, comprises: a first conductive layer:
a first pillar layer formed on the first conductive layer: a first package body encapsulating the first conductive layer and the first pillar layer: and
a second conductive layer electrically connecting to the first pillar layer: a first electronic component disposed above the second conductive layer of the package substrate:
a second package body encapsulating the first electronic component and the second conductive layer;
a second pillar layer formed on the second conductive layer of the semiconductor package; and
a third electronic component disposed above the second package body and electrically connecting to the package substrate through the second pillar layer; wherein the second package body further encapsulates the second pillar layer;

an interposer disposed on the second package body and electrically connecting to the package substrate through the second pillar layer;
wherein the third electronic component is disposed on and electrically connecting to the interposer.

19. The semiconductor device as claimed in claim 10 , further comprises:
a fourth conductive layer;
wherein the second pillar layer connects the fourth conductive layer to the second conductive layer, the second package, body encapsulates the second pillar layer and the fourth conductive layer, and the third electronic component is disposed on and electrically connecting to the fourth conductive layer.

Assignees

• Mediatek Inc

Inventors

• Hsu Wen-Sung
• Lin Shih-Chin
• Cheng Tao
• Chang Andrew C

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title