Array substrate, fabricating method thereof and display device

Patent metadata

Field	Value
Publication number	US-10254876-B2
Application number	US-201514914399-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Mar 6, 2015
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

An array substrate, a fabricating method thereof and a display device, the fabricating method comprises forming a plurality of touch electrodes on a base substrate, a plurality of touch electrode leads for leading out signals of the touch electrodes and an array structure comprising a plurality of conducting structures. At least part of touch electrode leads and at least one of the conducting structures are disposed in a same layer and made from a same material. The fabricating method can reduce the amount of masks used in the fabricating process of the array substrate.

First claim

The invention claimed is:

1. An array substrate comprising:
a base substrate;
a plurality of touch electrodes disposed on the base substrate;
a plurality of touch electrode leads disposed on the base substrate and configured for leading out signals of the touch electrodes respectively; and
an array structure disposed on the base substrate comprising a plurality of conducting structures; wherein
at least part of each touch electrode lead and at least one of the conducting structures are disposed in a same layer and are made from a same material, the array substrate further comprises a plurality of gate lines and a plurality of data lines which are disposed on the base substrate and are insulated from the touch electrode leads, each touch electrode lead comprises at least two first linear portions and at least one first bridging portion,
wherein
the at least two first linear portions and the gate lines are disposed in a same layer; the touch electrode lead intersects with at least one of the gate lines, and two adjacent first linear portions are connected through a first bridging portion at an intersection of the touch electrode lead with the gate line; or
the at least two first linear portions and the data lines are disposed in a same layer; the touch electrode lead intersects with at least one of the data lines, and two adjacent first linear portions are connected through a first bridging portion at an intersection of the touch electrode lead with the data line.

2. The array substrate according to claim 1 , wherein the array structure comprises a plurality of thin film transistors; each thin film transistor comprises a gate electrode, a source electrode and a drain electrode, and the gate electrode, the source electrode and the drain electrode belong to the conducting structures.

3. The array substrate according to claim 2 , wherein the array structure further comprises a plurality of shielding layers; each shielding layer is disposed between an active layer of each thin film transistor and the base substrate, and the shielding layers belong to the conducting structures.

4. The array substrate according to claim 2 , wherein each touch electrode lead and one of the conducting structures are disposed in a same layer and are made from a same material, and each touch electrode lead is in a one-piece structure.

5. The array substrate according to claim 1 , wherein
if the at least two first linear portions and the gate lines are disposed in a same layer, the first linear portions, the gate lines and the gate electrodes are disposed in a same layer and are made from a same material;
if the at least two first linear portions and the data lines are disposed in a same layer, the first linear portions, the data lines, the source electrodes and the drain electrodes are disposed in a same layer and are made from a same material.

6. The array substrate according to claim 1 , wherein
if the at least two first linear portions and the gate lines are disposed in a same layer, the first bridging portions, the source electrodes and the drain electrodes are disposed in a same layer and are made from a same material;
if the at least two first linear portions and the data lines are disposed in a same layer, the first bridging portions and the gate electrodes are disposed in a same layer and are made from a same material.

7. The array substrate according to claim 1 , wherein the array substrate further comprises a plurality of shielding layers, each shielding layer is disposed between an active layer of each thin film transistor and the base substrate, and the shielding layers belong to the conducting structures;
the first bridging portions and the shielding layers are disposed in a same layer and are made from a same material.

8. The array substrate according to claim 1 , wherein
an active layer of each thin film transistor comprises an active region, a source doped region and a drain doped region, and the source electrode and the drain electrode contact with the source doped region and the drain doped region through first via holes respectively;
the first bridging portions are connected to first linear portions through second via holes, and the layer in which at least part of the second via holes are formed is same to the layer in which at least part of the first via holes are formed.

9. The array substrate according to claim 1 , further comprising a common electrode layer disposed on the base substrate, wherein the touch electrodes are disposed in the common electrode layer.

10. The array substrate according to claim 9 , wherein the touch electrode leads are disposed between the common electrode layer and the base substrate.

11. An array substrate, comprising:
a base substrate;
a plurality of touch electrodes disposed on the base substrate;
a plurality of touch electrode leads disposed on the base substrate and configured for leading out signals of the touch electrodes respectively; and
an array structure disposed on the base substrate comprising a plurality of conducting structures; wherein
at least part of each touch electrode lead and at least one of the conducting structures are disposed in a same layer and are made from a same material;
each touch electrode lead comprises a linear portion and a bridging portion, and the bridging portion connects a touch electrode corresponding to the touch electrode lead to the linear portion;
the array substrate further comprises a passivation layer on the base substrate; and in a direction perpendicular to the base substrate, the passivation layer is between the linear portion of the touch electrode lead and the touch electrode corresponding to the touch electrode lead;
the array structure comprises a plurality of thin film transistors and a plurality of first electrodes connected with the plurality of thin film transistors respectively, and the plurality of conducting structures comprise the plurality of first electrodes; and
the bridging portion and each of the plurality of first electrodes are disposed in a same layer and are made from a same material.

12. The array substrate according to claim 11 , wherein the linear portion is disposed between the layer in which the first electrodes are disposed and the base substrate.

13. The array substrate according to claim 11 , further comprising a common electrode layer disposed on the base substrate, wherein the touch electrodes are disposed in the common electrode layer.

14. The array substrate according to claim 13 , wherein the linear portion is disposed between the layer in which the first electrodes are disposed and the common electrode layer, and the first electrodes are pixel electrodes.

15. A display device comprising an array substrate according to claim 1 .

16. A fabricating method of an array substrate comprising:
forming a plurality of touch electrodes on a base substrate;
forming a plurality of touch electrode leads on the base substrate for leading out signals of the touch electrodes; and
forming an array structure comprising a plurality of conducting structures on the base substrate; wherein
at least part of each touch electrode lead and at least one of the conducting structures are formed in a same mask process;
each touch electrode lead is insulated from gate lines and data lines, and each touch electrode lead intersects with at least one of the gate lines or data lines;
each touch electrode lead comprises at least two first linear portion and at least one bridging portion,
wherein
the at least two first linear portions and the gate lines are disposed in a same layer; the touch

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Lu Youqiang
• Qi Xiaojing
• Wang Zhidong
• Wang Jing

Classifications

• G06F2203/04111

  Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate · CPC title

• H01L27/124

  Electricity · mapped topic

• H01L27/1288

  Electricity · mapped topic

• H01L29/78675

  Electricity · mapped topic

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title