In-cell touch panel and display device

Patent metadata

Field	Value
Publication number	US-9519374-B2
Application number	US-201414443561-A
Country	US
Kind code	B2
Filing date	Sep 20, 2014
Priority date	May 30, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

An in-cell touch panel and a display device are disclosed. The in-cell touch panel includes: an upper substrate and a lower substrate arranged opposite to each other, a plurality of mutually independent self-capacitance electrodes arranged in the same layer, and a plurality of leads configured to connect the self-capacitance electrodes to a touch detection chip. The self-capacitance electrodes and the plurality of leads are arranged in different layers; an interlayer insulating layer is disposed between the self-capacitance electrodes and the leads; each self-capacitance electrode is electrically connected with the lead via a through hole running through the interlayer insulating layer; and the interlayer insulating layer is provided with recessed portions at overlapped areas of the self-capacitance electrodes and the leads other than the leads electrically connected with the self-capacitance electrodes. Therefore, the uniformity of display images of the touch panel can be improved.

First claim

The invention claimed is:

1. An in-cell touch panel, comprising: an upper substrate and a lower substrate arranged opposite to each other, a plurality of mutually independent self-capacitance electrodes arranged in a same layer, and a plurality of leads configured to connect the self-capacitance electrodes to a touch detection chip, wherein
the self-capacitance electrodes and the leads are disposed on one side of the upper substrate facing the lower substrate or one side of the lower substrate facing the upper substrate;
the self-capacitance electrodes and the leads are arranged in different layers, and an interlayer insulating layer is disposed between the self-capacitance electrodes and the leads; and
the self-capacitance electrodes are electrically connected with the leads via through holes running through the interlayer insulating layer; and the interlayer insulating layer is provided with recessed portions at overlapped areas of the self-capacitance electrodes and the leads other than the leads electrically connected with the self-capacitance electrodes.

2. The in-cell touch panel according to claim 1 , wherein the through holes and the recessed portions have consistent cross sectional shape and are uniformly distributed in the interlayer insulating layer.

3. The in-cell touch panel according to claim 2 , wherein the self-capacitance electrodes are combined into a common electrode layer disposed on one side of the lower substrate facing the upper substrate; and in a display period, common electrode signals are applied to the self-capacitance electrodes.

4. The in-cell touch panel according to claim 2 , wherein the self-capacitance electrodes and pixel electrodes on the lower substrate are arranged in a same layer; and a pattern of the self-capacitance electrode is disposed at a gap between two adjacent pixel electrodes.

5. The in-cell touch panel according to claim 2 , further comprising: gate signal lines and data signal lines which intersect each other and are disposed between the lower substrate and a layer provided with the self-capacitance electrodes, in which two adjacent gate signal lines and adjacent data signal lines surround a sub-pixel; and
an extension direction of the leads is the same as that of the gate signal lines or the data signal lines.

6. The in-cell touch panel according to claim 5 , wherein two adjacent rows of pixels are taken as a pixel group, two gate signal ones are disposed between the two adjacent rows of pixels and configured to provide gate scanning signals for the two adjacent rows of pixels respectively; and
the leads are disposed at gaps between adjacent pixel groups and arranged in a same layer as the gate signal lines.

7. The in-cell touch panel according to claim 6 , wherein a layer provided with the gate signal lines is disposed between the lower substrate and a layer provided with the data signal lines;
first conducting portions and second conducting portions are arranged hi a same layer as the data signal lines;
the self-capacitance electrodes and corresponding leads are respectively electrically connected with the first conducting portions;
the self-capacitances are electrically connected with the second conducting portions through the recessed portions; and the leads and the second conducting portions are insulated from each other.

8. The in-cell touch panel according to claim 5 , wherein two gate signal ones are disposed between adjacent rows of pixels; every two adjacent rows of pixels are taken as a pixel group and share a data signal line disposed between the two adjacent rows of pixels; and
the leads are disposed at gaps between adjacent pixel groups and arranged in a same layer as the data signal ones.

9. The in-cell touch panel according to claim 2 , further comprising: a touch detection chip configured to determine a touch position by detection of capacitance variation of the self-capacitance electrode in a touch period.

10. The in-cell touch panel according to claim 1 , wherein the self-capacitance electrodes are combined into a common electrode layer disposed on one side of the lower substrate facing the upper substrate; and in a display period, common electrode signals are applied to the self-capacitance electrodes.

11. The in-cell touch panel according to claim 10 , further comprising: gate signal lines and data signal lines which intersect each other and are disposed between the lower substrate and a layer provided with the self-capacitance electrodes, in which two adjacent gate signal lines and adjacent data signal lines surround a sub-pixel; and
an extension direction of the leads is the same as that of the gate signal lines or the data signal lines.

12. The in-cell touch panel according to claim 10 , further comprising: a touch detection chip configured to determine a touch position by detection of capacitance variation of the self-capacitance electrode in a touch period.

13. The in-cell touch panel according to claim 1 , wherein the self-capacitance electrodes and pixel electrodes on the lower substrate are arranged in a same layer; and a pattern of the self-capacitance electrode is disposed at a gap between two adjacent pixel electrodes.

14. The in-cell touch panel according to claim 13 , further comprising: gate signal lines and data signal lines which intersect each other and are disposed between the lower substrate and a layer provided with the self-capacitance electrodes, in which two adjacent gate signal lines and adjacent data signal lines surround a sub-pixel; and
an extension direction of the leads is the same as that of the gate signal lines or the data signal lines.

15. The in-cell touch panel according to claim 1 , further comprising: gate signal lines and data signal lines which intersect each other and are disposed between the lower substrate and a layer provided with the self-capacitance electrodes, in which two adjacent gate signal lines and adjacent data signal lines surround a sub-pixel; and
an extension direction of the leads is the same as that of the gate signal lines or the data signal lines.

16. The in-cell touch panel according to claim 15 , wherein two adjacent rows of pixels are taken as a pixel group, two gate signal lines are disposed between the two adjacent rows of pixels and configured to provide gate scanning signals for the two adjacent rows of pixels respectively; and
the leads are disposed at gaps between adjacent pixel groups and arranged in a same layer as the gate signal lines.

17. The in-cell touch panel according to claim 16 , wherein a layer provided with the gate signal lines is disposed between the lower substrate and a layer provided with the data signal lines;
first conducting portions and second conducting portions are arranged in a same layer as the data signal lines;
the self-capacitance electrodes and corresponding leads are respectively electrically connected with the first conducting portions;
the self-capacitances are electrically connected with the second conducting portions through the recessed portions; and the leads and the second conducting portions are insulated from each other.

18. The in-cell touch panel according to claim 15 , wherein two gate signal lines are disposed between adjacent rows of pixels: every two adjacent rows of pixels are taken as a pixel group and share a data signal line disposed between the two adjacent rows of pixels; and
the leads are disposed at gaps between adjacent pixel groups and arranged in a same layer as the data signal lines.

19. The in-cell touch panel according to

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Liu Yingming
• Dong Xue
• Xue Hailin
• Wang Haisheng
• Wang Lei
• Yang Shengji
• Liu Hongjuan

Classifications

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title

• G09G2310/0202

  Addressing of scan or signal lines · CPC title

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title