Cascode amplifier bias circuits

Patent metadata

Field	Value
Publication number	US-10250199-B2
Application number	US-201615268229-A
Country	US
Kind code	B2
Filing date	Sep 16, 2016
Priority date	Sep 16, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

First claim

What is claimed is:

1. An amplifier circuit including:
(a) a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit;
(c) a closed loop bias control circuit, having at least one input coupled to the cascode reference circuit and an output coupled to the gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit, responsive to variations in voltage and/or current in the cascode reference circuit to output an adjustment gate bias voltage applied to the respective gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value; and
(d) a respective decoupling network coupled between corresponding gates of each of the bottom two FET stages of the cascode amplifier, wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates.

2. An amplifier circuit including:
(a) a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit; and
(c) a current source, coupled to the drain of the top FET stage of the cascode reference circuit and to the respective gates of the bottom FET stages of the cascode reference circuit and the cascode amplifier; and
(d) a respective decoupling network coupled between corresponding gates of each of the bottom two FET stages of the cascode amplifier, wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates;

wherein the respective gates of the bottom FET stages of the cascode reference circuit and the cascode amplifier are responsive to variations in voltage in the cascode reference circuit such that the mirror current in the cascode reference circuit is forced to be approximately equal to a selected current value.

3. The invention of claim 1 , wherein the corresponding drain voltages of the bottom FET stage of the cascode amplifier and the cascode reference circuit are approximately the same.

4. The invention of claim 1 , wherein the cascode reference circuit is a split cascode reference circuit.

5. The invention of claim 1 , further including an input impedance matching network coupled to the input of the bottom FET stage and configured to be coupled to the RF input signal to be amplified.

6. The invention of claim 1 , further including an output impedance matching network coupled to the output.

7. An amplifier circuit including:
(a) a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit
(c) a closed loop bias control circuit, having at least one input coupled to the cascode reference circuit and an output coupled to the gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit, responsive to variations in voltage and/or current in the cascode reference circuit to output an adjustment gate bias voltage applied to the respective gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value;
(d) a degeneration inductor coupled between the source of the bottom FET stage of the cascode amplifier and RF ground, the degeneration inductor having a resistance Rdeg; and
(e) a compensation resistor coupled between the source of the bottom FET stage of the cascode reference circuit and RF ground, the compensation resistor having a resistance Rcomp such that the voltage at the source of the bottom FET stage of the cascode reference circuit closely approximates the voltage at the source of the bottom FET stage of the cascode amplifier.

8. The invention of claim 1 , wherein the input to the bottom FET stage is coupled to the gate of the bottom FET stage.

9. The invention of claim 1 , wherein the input to the bottom FET stage is coupled to the source of the bottom FET stage.

10. The invention of claim 1 , further including a source voltage, coupled to the cascode amplifier and the cascode reference circuit, having a range of about 0.4V to about 4.5V.

11. The invention of claim 1 , further including a bias voltage, coupled to the gates of the cascode amplifier, having a range of about 0.4V to about 4.5V.

12. The invention of claim 1 , wherein the RF input signal includes frequencies from and above about 100 MHz.

13. The invention of claim 1 , wherein the FETs in the cascode amplifier and in the cascode reference circuit have gate lengths less than about 1 μm.

14. The invention of claim 7 , wherein the corresponding drain voltages of the bottom FET stage of the cascode amplifier and the cascode reference circuit are approximately the same.

15. The invention of claim 7 , wherein the cascode reference circuit is a split cascode reference circuit.

16. The invention of claim 7 , further including an input impedance matching network coupled to the input of the bottom FET stage and configured to be coupled to the RF input signal to be amplified.

17. The invention of claim 7 , further including an output impedance matching network coupled to the output.

18. The invention of claim 7 , further including a respective decoupling network coupled between corresponding gates of each of the bottom two FET stages of the cascode amplifier.

19. The invention of c

Assignees

• Psemi Corp

Inventors

• Klaren Jonathan
• Wagh Poojan
• Kovac David
• Shapiro Eric S
• Calanca Neil
• Nobbe Dan William
• Murphy Christopher
• Englekirk Robert Mark
• Ayranci Emre
• Bargroff Keith
• Ranta Tero Tapio

Classifications

• H03F3/195 Primary

  in integrated circuits · CPC title

• H03F3/245

  with semiconductor devices only · CPC title

• H03F2200/555

  A voltage generating circuit being realised for biasing different circuit elements · CPC title

• H03F2200/222

  A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier · CPC title

• H03F2200/399

  A parallel resonance being added in shunt in the output circuit, e.g. base, gate, of an amplifier stage · CPC title