Amplifiers and related biasing methods and devices

Patent metadata

Field	Value
Publication number	US-9509263-B2
Application number	US-201514622650-A
Country	US
Kind code	B2
Filing date	Feb 13, 2015
Priority date	Sep 1, 2010
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Biasing methods and devices for amplifiers are described. The described methods generate bias voltages proportional to the amplifier output voltage to control stress voltages across transistors used within the amplifier.

First claim

What is claimed is:

1. A biasing method for an amplifier, the biasing method comprising:
providing an amplifier comprising a first plurality of devices arranged in a first cascode configuration;
supplying the amplifier with a positive supply voltage and a negative supply voltage;
sensing a voltage at an amplifier node coupled to the first cascode configuration through a sensing device;
based on the sensing, generating, via a second plurality of devices arranged in a second cascode configuration and a plurality of series-connected resistors coupled to the second cascode configuration via the sensing device, a plurality of bias voltages;
based on the generating, biasing the first plurality of devices; and
based on the biasing, operating the amplifier with an increased voltage range of the voltage at the amplifier node, wherein
a voltage magnitude of the positive supply voltage is larger than a withstand voltage of: a) each device of the first plurality of devices, b) each device of the second plurality of devices, and c) the sensing device, and
a voltage magnitude of the negative supply voltage is larger than a withstand voltage of: a) each device of the first plurality of devices, b) each device of the second plurality of devices, and c) the sensing device.

2. The biasing method of claim 1 , wherein the biasing of the first plurality of devices is configured to provide an operation of each device of the first plurality of devices within a withstand voltage of the each device.

3. The biasing method of claim 1 , wherein:
the first cascode configuration comprises a first device of the first plurality of devices and a last device of the first plurality of devices,
during operation, the first cascode configuration provides a conduction path from the first device to the last device,
the amplifier node is coupled to the first device of the first cascode configuration,
one of the positive supply voltage and the negative supply voltage is coupled to the last device of the first cascode configuration; and
the biasing of the first plurality of devices further comprises evenly distributing a voltage across the first cascode configuration.

4. The biasing method of claim 3 , wherein selection of a number of the first plurality of devices is based on the withstand voltage of any one device of the first plurality of devices, the positive supply voltage, and the negative supply voltage.

5. The biasing method of claim 4 , wherein the withstand voltage is equal to or less than 4 volts, and the positive supply voltage and the negative supply voltage are equal to or larger than 10 volts in magnitude.

6. The biasing method of claim 5 , wherein the increased voltage range ranges from a high voltage limit approaching the positive supply voltage, to a low voltage limit approaching the negative supply voltage.

7. The biasing method of claim 1 , wherein the sensing of the voltage at the amplifier node further comprises:
biasing the sensing device using the voltage at the amplifier node;
based on the biasing of the sensing device, controlling a current through the second cascode configuration;
based on the controlling, providing a current flow through the second cascode configuration proportional to the voltage at the amplifier node, and
based on the providing, obtaining a voltage division among the plurality of series-connected resistors, thus generating the plurality of bias voltages.

8. The biasing method of claim 7 , wherein the voltage division is an equal voltage division.

9. The biasing method of claim 7 , wherein the amplifier node is an input common mode node of the amplifier.

10. The biasing method of claim 7 , wherein the amplifier node is an output node of the amplifier.

11. The biasing method of claim 1 , wherein the first plurality of devices of the first cascode configuration, the second plurality of devices of the second cascode configuration, and the sensing device are MOSFET devices.

12. A bias circuit connectable, during operation, to a node of an amplifier coupled to a first plurality of devices arranged in a first cascode configuration, the bias circuit comprising:
a sensing device coupled to the node of the amplifier;
a second plurality of devices arranged in a second cascode configuration;
a plurality of series-connected resistors coupled to the second cascode configuration via the sensing device;
wherein, during operation:
the sensing device senses a voltage at the node of the amplifier and provides a corresponding proportional current flow through the second cascode configuration and the plurality of series-connected resistors,
the current flow through the series-connected resistors provides biasing voltages to the first plurality of devices via a plurality of nodes of the series-connected resistors that increase an operating voltage range of the voltage at the node of the amplifier without overstress of the first plurality of devices, and
the bias circuit operates from a positive supply voltage and a negative supply voltage of the amplifier, wherein:
a voltage magnitude of the positive supply voltage and a voltage magnitude of the negative supply voltage are larger than a withstand voltage of: a) each of the first plurality of devices, b) each of the second plurality of devices, and c) the sensing device.

13. The bias circuit of claim 12 , wherein the biasing voltages to the first plurality of devices evenly distribute a voltage across the first cascode configuration.

14. The bias circuit of claim 12 , wherein a number of the second plurality of devices of the second cascode configuration is equal to a number of the first plurality of devices of the first cascode configuration.

15. The bias circuit of claim 14 , wherein the number is based on a withstand voltage of a device of the first plurality of devices and the operating voltage range of the voltage at the node of the amplifier.

16. The bias circuit of claim 15 , wherein the operating voltage range ranges from a high voltage limit approaching the positive supply voltage of the amplifier, to a low voltage limit approaching the negative supply voltage of the amplifier.

17. The bias circuit of claim 16 , wherein the withstand voltage is equal to or less than 4 volts, and the positive supply voltage and the negative supply voltage are equal to or larger than 10 volts in magnitude.

18. The bias circuit of claim 12 , wherein the node is an input common mode node of the amplifier.

19. The bias circuit of claim 12 , wherein the node is an output node of the amplifier.

20. The bias circuit of claim 12 , wherein the first plurality of devices of the first cascode configuration, the second plurality of devices of the second cascode configuration, and the sensing device are MOSFET devices.

Assignees

• Peregrine Semiconductor Corp

Inventors

• Lam Fleming

Classifications

• H03F1/0272 Primary

  by using a signal derived from the output signal · CPC title

• H03F3/45

  Differential amplifiers (differential sense amplifiers G11C7/062) · CPC title

• H03F2203/45311

  the common gate stage of a cascode dif amp being implemented by multiple transistors · CPC title

• H03F2203/45024

  the differential amplifier amplifying transistors are cascode coupled transistors · CPC title

• H03F2200/471

  the voltage being sensed · CPC title