Non-volatile memory system with serially connected non-volatile reversible resistance-switching memory cells

Patent metadata

Field	Value
Publication number	US-10249682-B2
Application number	US-201715684141-A
Country	US
Kind code	B2
Filing date	Aug 23, 2017
Priority date	Aug 23, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

First claim

What is claimed is:

1. A non-volatile storage apparatus, comprising:
a first plurality of serially connected non-volatile reversible resistance-switching memory cells comprising a dielectric region having a set of pockets, physically separate active regions positioned in the pockets and a barrier layer in contact with the active regions to form reversible resistance-switching interfaces;
a first plurality of word lines, each of the memory cells of the plurality are connected to a different word line of the first plurality of word lines, the word lines are surrounded by the dielectric region;
a first bit line connected to a first end of the first plurality of serially connected non-volatile reversible resistance-switching memory cells; and
a first switch connected to a second end of the first plurality of serially connected non-volatile reversible resistance-switching memory cells.

2. The non-volatile storage apparatus of claim 1 , wherein:
each of the memory cells comprises a first current path and a second current path;
the first current path is reversible resistance-switching; and
the second current path bypasses the first current path.

3. The non-volatile storage apparatus of claim 1 , wherein:
each of the memory cells includes a channel that comprises the second current path and a gate connected to a respective word line of the first plurality of word lines, the gate is configured to create a depletion region in the channel in response to a word line voltage, the depletion region steers current from the channel into the first current path.

4. The non-volatile storage apparatus of claim 1 , further comprising:
additional pluralities of serially connected non-volatile reversible resistance-switching memory cells, for each plurality of serially connected non-volatile reversible resistance-switching memory cells each of the memory cells is connected to a different word line of the first plurality of word lines;
additional bit lines connected to the additional pluralities of serially connected non-volatile reversible resistance-switching memory cells, different bit lines are connected to different pluralities of serially connected non-volatile reversible resistance-switching memory cells; and
additional switches connected to the additional pluralities of serially connected non-volatile reversible resistance-switching memory cells, different switches are connected to different pluralities of serially connected non-volatile reversible resistance-switching memory cells.

5. The non-volatile storage apparatus of claim 1 , wherein:
the first plurality of serially connected non-volatile reversible resistance-switching memory cells are vertically displaced above the switch.

6. The non-volatile storage apparatus of claim 1 , wherein the first plurality of serially connected non-volatile reversible resistance-switching memory cells comprises:
a plurality of vertically displaced reversible resistance-switching elements;
a plurality of vertically displaced control line layers, each control line layer positioned between two consecutive reversible resistance-switching elements, each control line layer comprising an offset layer and an associated word line layer that is part of a corresponding word line of the first plurality of word lines, the offset layer shields the associated word line layer form controlling one of the two consecutive reversible resistance-switching elements;
a vertical channel layer positioned between the vertically displaced reversible resistance-switching elements and the vertically displaced control line layers; and
a bit line connected to a first end of the channel layer.

7. The non-volatile storage apparatus of claim 1 , further comprising:
a sense amplifier connected to the first bit line.

8. The non-volatile storage apparatus of claim 1 , wherein:
the first plurality of serially connected non-volatile reversible resistance-switching memory cells include a common horizontal channel; and
the first plurality of serially connected non-volatile reversible resistance-switching memory cells are horizontally displaced.

9. The non-volatile storage apparatus of claim 1 , wherein the memory cells further comprise:
a channel layer positioned between the word lines and the active regions, the channel layer at least partially positioned in the pocket.

10. The non-volatile storage apparatus of claim 9 , wherein:
the channel layer is positioned along three sides of one of the active regions.

11. A non-volatile storage apparatus, comprising:
a plurality of vertically displaced reversible resistance-switching elements that are physically separate from each other;
a plurality of vertically displaced control line layers, each control line layer positioned vertically between two consecutive reversible resistance-switching elements, each control line layer comprising an offset layer and an associated word line layer, the offset layer shields the associated word line layer form controlling one of the two consecutive reversible resistance-switching elements;
a vertical channel layer positioned between the vertically displaced reversible resistance-switching elements and the vertically displaced control line layers; and
a bit line connected to a first end of the channel layer;
each control line layer is positioned between an upper reversible resistance-switching element and a lower reversible resistance-switching element;
the offset layer for each control line layer is on a first side of the control line layer facing the lower reversible resistance-switching element such that the word line layer is unable to selectively control the lower reversible resistance-switching element;
the word line layer for each control line layer is on a second side of the control line layer facing the upper reversible resistance-switching element such that the word line layer is configured to selectively control the upper reversible resistance-switching element.

12. The non-volatile storage apparatus of claim 11 , further comprising:
a dielectric region includes a plurality of pockets, the control line layers are positioned in the dielectric region, the reversible resistance-switching elements are at least partially positioned in the pockets, the channel layer is at least partially positioned in the pockets.

13. The non-volatile storage apparatus of claim 11 , wherein:
each word line layer is configured to create a depletion region in the channel layer in order to divert current from the channel layer through one of the reversible resistance-switching elements.

14. A non-volatile storage apparatus, comprising:
a switch;
a core comprising two vertical pillars of barrier layers separated by dielectric material positioned above the switch;
a first plurality of vertically displaced active layers positioned on a first side of the core in contact with one of the vertical pillars of barrier layers;
a second plurality of vertically displaced active layers positioned on a second side of the core in contact with one of the vertical pillars of barrier layers;
a first vertical channel connected to the switch and positioned along a portion of the first side of the core, the first vertical channel at least partially surrounding each of the first plurality of vertically displaced active layers on three sides of each of the first plurality of vertically displaced active layers; and
a second vertical channel connected to the switch and positioned along a portion of the second side of the core, the second vertical channel at least partially surrounding each of the second plurality of vertically displaced active layers on three sides of

Assignees

• Sandisk Technologies Llc

Inventors

• Franca-Neto Luiz M
• Apodaca Mac D
• Petti Christopher J

Classifications

• G03G5/024

  Photoelectret layers · CPC title

• G11C13/003

  Cell access · CPC title

• H01L27/2481 Primary

  Electricity · mapped topic

• H01L29/78603

  Electricity · mapped topic

• H01L27/10891

  Electricity · mapped topic