Shared-gate vertical-TFT for vertical bit line array

Patent metadata

Field	Value
Publication number	US-9236122-B2
Application number	US-201414340454-A
Country	US
Kind code	B2
Filing date	Jul 24, 2014
Priority date	Jul 31, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.

First claim

What is claimed is:

1. A non-volatile storage system, comprising:
a substrate;
a monolithic three dimensional arrangement of memory cells positioned above and not in the substrate;
a plurality of word lines connected to the memory cells;
a plurality of global bit lines;
a plurality of vertically oriented bit lines connected to the memory cells; and
a plurality of double gated vertically oriented select devices that are above and not in the substrate, the double gated vertically oriented select devices are connected to the vertically oriented bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertically oriented bit lines are in communication with the global bit lines, each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate with only one gate on each of two sides of the double gated vertically oriented select device so that both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.

2. The non-volatile storage system of claim 1 , wherein:
the first of the two gates is adjacent to a drain of the double gated vertically oriented select device but not adjacent to a source of the double gated vertically oriented select device and a second of the two gates is adjacent to the source of the double gated vertically oriented select device but not adjacent to the drain of the double gated vertically oriented select device.

3. The non-volatile storage system of claim 2 , wherein:
the double gated vertically oriented select devices each comprise only one transistor.

4. The non-volatile storage system of claim 3 , wherein:
the one transistor includes two source/drain regions;
during a programming operation, the two gates create two channels, one channel for each gate; and
during the programming operation, the two source/drain regions are depleted and short the two channels.

5. The non-volatile storage system of claim 1 , wherein:
each double gated vertically oriented select device includes two middle conductivity regions each between source/drain regions; and
a first of the two gates adjacent to a first conductivity region of the two middle conductivity regions but not adjacent to a second conductivity region of the middle conductivity regions and a second of the two gates adjacent to the second conductivity region of the middle conductivity regions but not adjacent to the first conductivity region of the conductivity regions.

6. The non-volatile storage system of claim 5 , wherein:
the double gated vertically oriented select devices each comprise two transistors in series;
the first of the two gates is part of one of the two transistors;
the second of the two gates is part of a second of the two transistors so that current from a selected global bit lines passes through both of the two transistors when the double gated vertically oriented select device is in the “on” condition.

7. The non-volatile storage system of claim 5 , wherein:
the first of the two gates creates a first channel in the first conductivity region of the two middle conductivity regions; and
the second of the two gates creates a second channel in the second conductivity region of the two middle conductivity regions.

8. The non-volatile storage system of claim 1 , wherein:
each double gated vertically oriented select device includes two middle conductivity regions each between source/drain regions; and
both of the two gates are adjacent both of the two middle conductivity regions.

9. The non-volatile storage system of claim 8 , wherein:
the double gated vertically oriented select devices each comprise two transistors in series;
the first of the two gates is part of one of the two transistors;
the second of the two gates part of a second of the two transistors so that current from a selected global bit lines passes through both of the two transistors when the double gated vertically oriented select device is in the “on” condition.

10. The non-volatile storage system of claim 8 , wherein:
the first of the two gates creates channels in both of the two middle conductivity regions; and
the second of the two gates creates channels in both of the two middle conductivity regions.

11. The non-volatile storage system of claim 1 , wherein:
the double gated vertically oriented select devices include a transistor with a vertically oriented channel.

12. The non-volatile storage system of claim 1 , wherein:
the two gates are positioned between and below vertically oriented bit lines.

13. The non-volatile storage system of claim 1 , wherein:
the memory cells in combination with the vertically oriented bit lines and the word lines form a continuous mesh.

14. The non-volatile storage system of claim 1 , wherein:
the monolithic three dimensional arrangement of memory cells is an array of variable resistance memory elements.

15. The non-volatile storage system of claim 1 , further comprising:
control circuitry for operating the memory cells, active areas of the memory cells are disposed above the substrate.

16. A method of operating non-volatile storage, comprising:
providing an unselected word line voltage to unselected word lines connected to a monolithic three dimensional arrangement of memory cells positioned above and not in a substrate;
providing a selected word line voltage to a selected word line connected to the monolithic three dimensional arrangement of memory cells;
providing a data signal on a global bit line, the global bit line connected to a double gated vertically oriented select devices that is above and not in the substrate, the double gated vertically oriented select device is connected to a vertically oriented bit line and the global bit lines so that when the double gated vertically oriented select device is activated the vertically oriented bit line is in communication with the global bit line, the double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate with only one gate on each of two sides of the double gated vertically oriented select device so that both gates for the double gated vertically oriented select device need be at an “on” condition for the double gated vertically oriented select devices to be activated; and
activating the double gated vertically oriented select device by applying an “on” signal to both gates.

17. The method of claim 16 , wherein:
the first of the two gates is adjacent to a drain of the double gated vertically oriented select device but not adjacent to a source of the double gated vertically oriented select device and a second of the two gates is adjacent to the source of the double gated vertically oriented select device but not adjacent to the drain of the double gated vertically oriented select device.

18. The method of claim 16 , wherein:
each double gated vertically oriented select device includes two middle conductivity regions each between source/drain regions; and
a first of the two gates adjacent to a first conductivity region of the two middle conductivity regions but not adjacent to a second conductivity region of the middle conductivity regions and a second of the two gates adjacent to the second conductivity region of the middle conductivity regions but not adjacent to the first conductivity region of the middle conductivity regions.

19. The m

Assignees

• Sandisk 3D Llc
• Sandisk 3D Llc

Inventors

• Yan Tianhong
• Samachisa George
• Liu Tz-Yi
• Chen Tim
• Ratnam Perumal

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H01L45/08

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L27/0688

  Electricity · mapped topic

• G11C2207/005

  Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines · CPC title