Semiconductor device

Patent metadata

Field	Value
Publication number	US-10249627-B2
Application number	US-201715621315-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Nov 3, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A semiconductor device is provided. The semiconductor device includes an upper interlayer insulating layer disposed on a substrate. A first electrode spaced apart from the upper interlayer insulating layer is disposed on the substrate. A contact structure penetrating the upper interlayer insulating layer is disposed on the substrate. An upper support layer having a first portion covering an upper surface of the upper interlayer insulating layer, to surround an upper side surface of the contact structure, and a second portion extending in a horizontal direction from the first portion and surrounding an upper side surface of the first electrode, is disposed. A dielectric conformally covering the first electrode and a second electrode on the dielectric are disposed.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an upper interlayer insulating layer disposed on a substrate;
a first electrode disposed on the substrate and spaced apart from the upper interlayer insulating layer;
a contact structure disposed on the substrate and penetrating the upper interlayer insulating layer;
an upper support layer including a first portion covering an upper surface of the upper interlayer insulating layer and surrounding an upper side surface of the contact structure, and a second portion extending in a horizontal direction from the first portion and surrounding an upper side surface of the first electrode;
a dielectric conformally covering the first electrode; and
a second electrode on the dielectric,
wherein the second electrode covers an upper surface of the second portion of the upper support layer, to extend upwardly from the first portion of the upper support layer, and
wherein a portion of the second electrode, which extends upwardly from the first portion of the upper support layer, is located at a level higher than that of an upper surface of the contact structure.

2. The semiconductor device of claim 1 , wherein the upper support layer has a thickness in an upward direction perpendicular to the substrate smaller than a thickness of the upper interlayer insulating layer in the upward direction perpendicular to the substrate and is formed of a material having etch selectivity with respect to the upper interlayer insulating layer.

3. The semiconductor device of claim 1 , further comprising a lower structure on the substrate,
wherein the lower structure includes a first contact area, a bit line adjacent to the first contact area, a second contact area, and a peripheral gate electrode adjacent to the second contact area,
the first electrode being disposed on the first contact area,
the contact structure being disposed on the second contact area,
at least a portion of the peripheral gate electrode being disposed in a same plane as the bit line.

4. The semiconductor device of claim 1 , further comprising:
a lower interlayer insulating layer disposed between the substrate and the upper interlayer insulating layer and spaced apart from the first electrode; and
a lower support layer interposed between the lower interlayer insulating layer and the upper interlayer insulating layer, extending in a horizontal direction, and surrounding a portion of a side surface of the first electrode.

5. The semiconductor device of claim 4 , wherein a side surface of the lower interlayer insulating layer opposing the first electrode has a curvature greater than that of a side surface of the upper interlayer insulating layer opposing the first electrode.

6. The semiconductor device of claim 4 , wherein the contact structure includes: a contact plug continuously penetrating the first portion of the upper support layer, the upper interlayer insulating layer, the lower support layer, and the lower interlayer insulating layer; and a barrier layer surrounding a side surface of the contact plug.

7. The semiconductor device of claim 4 , wherein the lower interlayer insulating layer includes a lower layer and an upper layer, and
a width of the contact structure is extended in a region adjacent to a boundary of the lower layer and the upper layer.

8. The semiconductor device of claim 1 , further comprising a space between the first electrode and a side surface of the upper interlayer insulating layer opposing the first electrode,
wherein a second portion of the second electrode is disposed inside the space, and
a portion of the dielectric surrounds the second electrode inside the space and is in contact with the side surface of the upper interlayer insulating layer.

9. The semiconductor device of claim 1 , further comprising a dam structure disposed between the first electrode and the contact structure,
the first electrode being disposed in a memory cell array region of the substrate,
the contact structure being disposed in a peripheral circuit region of the substrate,
the dam structure being disposed between the memory cell array region and the peripheral circuit region and surrounding the cell array region,
the dam structure, the contact structure, and the upper support layer having upper surfaces coplanar with each other.

10. A semiconductor device, comprising:
an interlayer insulating layer disposed on a substrate;
an upper support layer including a first portion covering an upper surface of the interlayer insulating layer and a second portion formed to extend in a horizontal direction from the first portion;
a contact structure penetrating the first portion of the upper support layer and the interlayer insulating layer; and
a data storage element disposed on the substrate and spaced apart from the contact structure,
the data storage element including a first electrode spaced apart from the interlayer insulating layer, a dielectric on the first electrode, and a second electrode on the dielectric,
an upper side surface of the first electrode being surrounded by the second portion of the upper support layer,
an upper side surface of the contact structure being surrounded by the first portion of the upper support layer and being in contact with the first portion,
at least a portion of the upper side surface of the first electrode being in contact with the second portion of the upper support layer,
the second electrode covering an upper surface of the second portion of the upper support layer.

11. The semiconductor device of claim 10 , further comprising a dam structure disposed between the first electrode and the contact structure and surrounding the first electrode,
wherein the dam structure has an upper surface coplanar with an upper surface of the contact structure.

12. The semiconductor device of claim 11 , wherein the second electrode extends upwardly from the dam structure, and
the dielectric extends between the second electrode and the dam structure.

13. The semiconductor device of claim 10 , wherein the contact structure includes a contact plug and a barrier layer surrounding a side surface of the contact plug, and
the contact plug continuously penetrates the first portion of the upper support layer and the interlayer insulating layer.

14. The semiconductor device of claim 10 , further comprising:
an inter-metal insulating layer disposed on the upper support layer, covering the second electrode, and formed of a dielectric having permittivity lower than that of the interlayer insulating layer;
a first interconnection structure penetrating the inter-metal insulating layer and electrically connected to the second electrode; and
a second interconnection structure penetrating the inter-metal insulating layer and electrically connected to the contact structure.

15. A semiconductor device, comprising:
a first interlayer insulating layer disposed on a substrate;
a second interlayer insulating layer on the first interlayer insulating layer;
a first support layer between the first interlayer insulating layer and the second interlayer insulating layer;
a second support layer on an upper surface of the second interlayer insulating layer;
a first electrode disposed on the substrate and spaced apart from the first and second interlayer insulating layers;
a contact structure disposed on the substrate and penetrating the first interlayer insulating layer, the first support layer, the second interlayer insulating layer and the second support layer;
a dielectric conformally covering the first electrode; and
a second electrode on the dielectric; and
a sp

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Jung Hoon
• Kim Dong Wan
• Kim Ji Hun
• Song Jae Joon
• Takeda Hiroshi

Classifications

• H01L27/10855

  Electricity · mapped topic

• H01L28/60

  Electricity · mapped topic

• H01L27/10814 Primary

  Electricity · mapped topic

• H01L28/87

  Electricity · mapped topic

• H10D1/716 Primary

  having vertical extensions · CPC title